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TPS2596: About VEN/UVLO and VOV maximum input voltage range

Tsukui Yusuke
Guru 21930 points
Part Number: TPS2596

Hi,

Customer is considering TPS2596.
However, TPS2596 has specifications that are inferior to TPS25921.
Absolute maximum input voltage range of the VEN/UVLO and VOV is 7V, which is lower than TPS25921.



Customer wants 21V, taking into account the breakdown of the resistor divider.
Could you tell us why the EN / UVLO and OVCSEL / OVLO pins have an absolute maximum rating of 7V?

Best Regards,
Yusuke

  • 0
    TI__Guru 57737 points

    Hi Yusuke,

    Your observation is correct. TPS2596 has EN / UVLO and OVCSEL / OVLO pin ratings are less when compared to that of TPS25921.

    These pins are designed to be low-voltage pins and hence you need to use resistor dividers to step down the voltage such that the max voltage these pins see is only 7V.

  • 0 in reply to Praveen GD
    Guru 21930 points

    Praveen-san,

    Thank you for your response.
    Is there any reason to lower the absolute maximum rating?

    Best Regards,
    Yusuke

  • 0 in reply to Tsukui Yusuke
    TI__Guru 57737 points

    Hi Yusuke,

    It is a cautious decision taken to lower the voltage ratings of these pins as many applications do not have high voltage requirement for these pins.

    For example,

    • The EN/UVLO, FLT/ pins in majority of the applications are pulled up by Vin (stepped down) or driven by GPIO of micro-controller/processor which operate at signal level voltages like 5V, 3.3V or 1.8V. 
    • OVSEL pin is either connected to GND or left floating. So, this pin need not be rated for 20V.

  • 0 in reply to Praveen GD
    TI__Guru 57737 points

    Hi Yusuke,

    Do let me know in case you have more questions. If you do not have more questions, can we close this thread ?

  • 0 in reply to Praveen GD
    Guru 21930 points

    Hi Praveen,

    Thank your for your response and comment.

    >The EN/UVLO, FLT/ pins in majority of the applications are pulled up by Vin (stepped down) or driven by GPIO of micro-controller/processor which operate at signal level voltages like 5V, 3.3V or 1.8V. 
    Customer is concerned about pulling up to Vin.
    For example, For example, consider the Input voltage = 12V pattern.
    In this case, when the voltage dividing resistor is destroyed, a voltage exceeding the absolute maximum rating of  EN/UVLO Pin is applied.
    I want your views on this pattern.
    Could you give me your advice.



    Best Regards,
    Yusuke

  • 0 in reply to Tsukui Yusuke
    TI__Guru 57737 points

    Hi Yusuke,

    In case, EN/UVLO is pulled up to Vin and the resistor divider is destroyed: If EN/UVLO sees a voltage greater than 7V, the IC can get damaged.

    I understand your use case and we will consider this as an input for our future IC development. Thanks!