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LM5025A: LM5025A question about Logic and CS1 pin?

Bob Lee62837
Mastermind 7230 points
Part Number: LM5025A

Dear support member,

My customers are in mass production using LM5025A.
This project is urgency.

I have a question.

（Question 1）
If H / L signal is entered in LOGIC,
What happens to the H / L signal from LOGIC?

（Question 2）
What are the conditions for the OR circuit to become H / L?

（Question3）
I want to check the voltage generated by the resistor at power-on with the CS1 pin, but the voltage value is 0V.

What is the cause?


I attached file about question.
Could you check it?

LM5025A_Question_191206.pdf


Best regard.
Bob Lee.

  • 0
    TI__Genius 13660 points

    Hi Bob, sorry for the delay response. I am looking at this question and will reply you soon. Thanks. —— Teng

  • 0 in reply to Teng Feng
    TI__Genius 13660 points

    Hi Bob,

     RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to control the duty cycle of the main switch output. The volt second clamp comparator also monitors the RAMP pin and if the ramp amplitude exceeds 2.5 V the present cycle is terminated. 

    If the sense voltage at the CS1 input exceeds 0.25 V the present power cycle is terminated (cycle-by-cycle current limit)

    The conditions that can change the output of OR gate contains UVLO, second-level current limit, thermal protection.
    CS1 pin is an input pin, in your schematic, CS1 pin is connected to GND, so there is no confusion that the voltage on the resister is 0. You can sense the current referring to the datasheet.

    Regards,

    Teng

  • 0 in reply to Teng Feng
    Mastermind 7230 points

    Dear Teng Feng,


    Thank you very much for your reply.

    Since only the text does not understanding,
    Could you explain it while writing it on the function block diagram?

    ex,
    Could you describe of function block diagram the output signal H/L according to the logic input signal H/L ?


    Best regard.
    Bob Lee.

  • 0 in reply to Bob Lee62837
    TI__Genius 13660 points

    Hi Bob, 

    I also can't see the inside circuit of LOGIC block.

    But from the block diagram, we can see that the output of LOGIC controls PWM output and SS function. and there are many input signals of LOGIC block, such as UVLO, Vcc UVLO, REFERENCE, RAMP, COMP, CS1, CS2 and  thermal protection.

    So to understand how LOGIC block works, what you need do is read datasheet carefully, to make clear that which signal will terminal PWM putput, which signal will charge or discharge SS pin,

    Regards,

    Teng