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WEBENCH® Tools/LP5912: LP5912-1.2DRVT, LP5912-1.8DRVT

Ramazan Kaan EREN33
Prodigy 40 points
Part Number: LP5912

Tool/software: WEBENCH® Design Tools

Hi experts,

i am using LP5912-1.2DRVT and LP5912-1.8DRVT fixed output DC-DC converters. in schematic i am using 5V input voltage and 1.2V, 1.8V output voltage but When i am simulating it in webench tool it constraints me to use lower input range(for 1.2V range is 1.6V-2.9V and for 1.8V range is 2V-3.8V). When i insert 4.7V- 5.5V range as input it automatically reduce this range and says " this voltage is out of input range" however it is stated in datasheet that this device can accept 1.6V-6.5V input range so i am doubted if i can use this device with 5V inputs. 

Another question is i am designing an FPGA board thats why regulators and power sources are very close. So i am using 10uF ceramic input and 4.7uF ceramic output capacitors. What do you think about stability and what do you prefer instead of this values?

Kind Regards  

  • 0
    TI__Mastermind 32480 points

    Hi Ramazan,

    When there is a discrepancy between the simulation model and the datasheet, the datasheet will always take precedence.
    In this case the simulation is in error.  The datasheet correctly states that the LP5912 can accept a 5V input supply.

    According to the datasheet, the output capacitor must remain within 1uF to 10uF to maintain stability.
    Using voltage bias and other tolerance effects from the capacitor datasheets, you may or may not fall within this range of stability, so you will need to do a brief review of your capacitors to confirm.
    Additionally you will need 5m ohms of ESR at a minimum.
    The effective ESR of parallel ceramics may come close to this minimum, even when accounting for PCB copper impedance.
    At a first order approximation you can use the ESR of each capacitor and treat it like parallel resistors, which divide down in value as you add additional capacitors in parallel.  A higher level approximation is to use the manufacturer capacitor models (if they exist for your capacitors) and simulate the parallel capacitor network to find the minimum ESR or impedance.

    Thanks,

    - Stephen