LMG1205HBEVM: HO Remains Mid-level During Falling HS Dead-time

Hello Jeff,

Thank you for your reply.

I am using the EPC9034 rev1.1 demo board with the LM5113 and our full bridge product with the LMG1205.

All bridge measurements are with the outputs unloaded, so it makes sense that HS stays high until LO rises, but HO staying mid-level during the dead-time is odd.

Both platforms exhibit very similar results. The images are from our product. I have also corrected the image labels. I apologize for the confusion it must have caused.

I had increased the dead-times to 40nS and saw no change in the 30mS no-load current. The mid-level stayed constant through the extended dead-time.

I am speculating that the excess current is not while HO is mid-level but rather shoot-through when LO comes up and pulls HS down.

We will get and test the LMG1205HBEVM if you suggest it may help.

Thank you for your help,

Dave

Delayed HS Gate Drop TransmitDriver.pdf

Hi Dave,

Thanks for the update.

Can you show a schematic or image of how the EPC board is being connected to your 1205 full bridge board? Highlighting the gate connection length.

This issue looks like long HO and LO gate connection is causing the switch node transition to be coupled to the gate loop.

Thanks,

Hello Jeff,

Here is a pdf with some layout layers, schematic of one half-bridge, and some pics for overall reference.

Thank you for your help,

Dave

Good morning Jeff, and thank you for your continued help.

I'm including the same pdf with the internal copper layers and screen shots of layers 1&2 and all layers with that net highlighted in that region.

There are five via sets in the stack-up:1-2 [laser via], 1-4, 5-8, 7-8, 1-8[also laser via].

Also, please consider the EPC9034 layout.It exhibits the same issue except it draws 110mA instead of 130mA with no load at 48V and 1MHzEPC903x_Rev1_1_Layout.pdf.

We are receiving the TI LMG1205HBEVM today to learn what we can.

Thank you Jeff,

Dave

Hi Dave,

thanks for the update, let me review the added documents.

Does the high-side of EPC2022's pin 29 directly connect to pin 30 (substrate) on the top layer?

it looks like the drain is pulled out to a via sticking out of the back of the GaN (Q1 and Q3) preventing this connection.

The substrate should connect to the source pins with low inductance to eliminate the GaN substrate to source parasitics.

Can you show me the issue waveforms for the EPC9034 board? can you show or explain how are you connecting your probes for this measurement? are you using pigtail probes with all probes referenced to the same driver ground?

You mentioned 5113 however I only see up1966 from the EPC board.

Thanks,

Hello Jeff,

Here is the Quick Start Guide for the EPC9034 rev1.1 with the LM5113.

5315.EPC9034_qsg_rev1p1.pdf

Here is an image of the channel B top copper showing pads 29 and 30 connected to the other source pads.

The center net on the bottom device is source and drain on the high side device.

I am working on the EPC9034 waveforms.

Thank you for your close attention to detail.

Dave

Jeff,

Here is how I am probing HS-GND and HO-GND on the two eval bds.EvalBdProbes.pdf

And here are the HS and HO waveforms for the two eval bds.

In case operating unloaded made a difference, I removed L1 from the LMGEVM bd to verify.

Mark G. at EPC claims the half bridge driver will not function unloaded.

Thank you Jeff,

DaveEvalBdWaveforms.pdf

Hello Jeff,

Thank you for your reply.

To improve the connection between pads 29 and 30, I can remove the extra drain via to the supply and connect them directly on both high side devices.

I can understand the importance of a low impedance substrate connection, especially for the gate circuit.

This might then reduce my 130mA to the EPC EVM's 110mA - since it has 29-30 direct connections.

It's interesting that this would not be visible on the gate voltage even though it is series with the gate in the device.

For a test, I will add a copper foil strip across the 29-30 gap. this should approximate the next revision surface trace and be far better than the vias to layer 4.

I should have data by mid-day.

Your shoot-through or ringing question has merit. Please help me with what ringing might be the cause.

I don't understand EPC's claim regarding the unloaded ability of the driver either.

But then, this whole conversation is about me learning.

Thank you again Jeff,

Dave

Thanks for the update Dave,

I was referring to the mid-way dip in the switching HO transition voltage as the ring. Its possible this glitch has something to do with the extra mA.

Let me know if you have any other issues or questions on LMG1205.

Thanks,

Hello Jeff,

We were not able to solder to the solder lines under the high-side devices to reduce the source-substrate impedance.

Addressing your question about the mid-level HO value:

Since it looks like a voltage divider, I considered the possibility that HOH and HOL could both be on during the dead-time.

With the voltage just above threshold, I added 5ohms to HOH.

This would reduce the voltage enough to solve the problem while also slowing the rise time. 

The result was that the mid-level voltage did not change.

On a different theory, the half-bridge output capacitance accounts for the current draw.

1400pF x 2 x 50V x 1MHz = 140mA , For the full-bridge board 2 x 140mA x 50V = 14W

While this accounts for the current, I would not expect the devices to heat as much as they do.

Our new-grad determined unintentional continuous operation quickly exceeds maximum temperature.

With those ideas presented, please advise me on reliability. 

I have estimated the HS rise time to be 5nS.

With an average current of 130mA, a repetition rate of 1MHz,

and a pulse width of 5nS, if I  assume current is uniform during the pulse, it would be 26A. 

I'd like to say that with the 90A/390A device ratings, 26A will not cause premature failure.

We have a 50V at 20A, 1KHz driver and this 50V at 3A, 1MHz driver, both with over 100K 10mS bursts.

The performance to this point is very acceptable, but I need to quantify the stress.

Can you help with this?

Thank you Jeff,

Dave

Hi Dave,

Thanks for the update,

Do you know the max temperature that the 1205 case sees? For how long does this temp occur?

Thanks,

Good morning Jeff,

The driver is heated by the FETs, but our transmission bursts are short with a low duty cycle.

We will not be seeing very much temperature rise.

Now that we know the current is inherent to the FET output capacitance the only issue I am concerned about is the transition stress.

The part is rated for 90A/390A, but I am sure is while fully enhanced. 

The stress from the current during transition is what I am asking you about.

For approx 2.5nS during the 5nS transition, the peak power is over 1KW.

So this would apply to all of these HEMT parts operating at 1MHz.

Are smaller parts, with higher on resistance used for smaller input and output capacitances?

Thank you Jeff,

Dave

Hello Jeff,

Please remove design related attachments from the public accessed website.

Specifically the pdfs with images of the board and gerbers,

Thank you Jeff,

Dave