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TPS68470: HLK_A and HCLK_B

Antony Lin
Genius 13480 points
Part Number: TPS68470

Hi,

Is there any possibility to achieve HLK_A and HCLK_B clock rate as listed below with source from either GPIO3 or crystal?  Or the clock rate of them must be in the range from 4M to 64MHz anyway?

1. HCLK_A: 24 MHz

2. HCLK_B: 32.768 KHz

 THanks!

 

Antony

  • 0
    TI__Expert 8730 points

    Hi,

    This device is being supported by my colleague in US and he will get back to you within 24 Hrs.

    Regards,

    Murthy

  • 0
    TI__Genius 10380 points

    Hi Antony,

    While the desired HCLK_A frequency of 24 MHz can be achieved, the HCLK_B frequency of 32.768 kHz cannot.

    From Section 8.3.2 and Figure 4 of the datasheet, HCLK_A and HCLK_B are referenced to the PLL_VCO_CLK frequency. PLL_VCO_CLK should be configured in the range of 32 MHz to 64 MHz. The largest divisor possible for the HCLK_A and HCLK_B outputs is 8, specified in the POSTDIV and POSTDIV2 registers. This results in the HCLK_A and HCLK_B frequency range of 4 MHz to 64 MHz, as you have mentioned. 

    Thanks,

    Gerard