UCC28780: ucc28780

Hello Robin,

Sorry for the mix-up with your last post, and resultant delay.

While reviewing your “ucc28780startup_gnmr.pptx” file I’ve come up with some major concerns with your high-side isolator biasing arrangement.

First off, I’d like to state that the overall biasing circuit(s) shown in “tidrvm3b28780scheval_DIODES.pdf” is a proven design used in many applications. The minor uncertainty of 2-V Zener drops is not important to the functioning, but some amount of voltage drop is necessary for reliability.

Secondly, the resolution of the .pptx file is low so many component values and part numbers are difficult to decipher. A clearer version with more resolution will be helpful in some review points.

1. In your implementation, you substitute a TL4051 for the usual 6.2V Zener to bias the NV6117 devices. I can’t read the resistor around it but the NV6117 datasheet calls for a nominal 6.2V at this pin. Assuming you set the TL4051 for 6.2V, there is no dropping Zener in series with the NV6117 VDD output and the ISO7710F VCC2 input. Bu the ISO part VDD abs max rating is 6V, so 6.2V will over stress this part and may be a reliability issue over the long term. That is why we put a 2-V drop in series, but the accuracy of the 2-V drop is not critical. Ideally, VCC2 should be 5V or less.

2. It is unclear if the values of VCC2 caps C9(?) and C15 are 1uF each or 1nF each. Neither are desirable; one being too big, the other too small. Too big takes too long to charge above UVLO after a long wait time coming from ASBP mode into AAM on a load step. Too small can have excess ripple voltage during switching. Please check the “tidrvm3b” file for proven values.

3. The low-side NV-FET doesn’t really need an isolator for PWML, it can drive the switch directly. If you are trying to match propagation delays with the high-side, that’s okay, but not really necessary. It is not clear where the low-side isolator VCC1 gets its bias voltage from, but it should be up in spec almost immediately after the UCC28780 VDD crests 17.5V. Because PWML switching will start as soon as HVG drops to 11V.

4. The high-side NV6117 gets VDD bias from transformer isolated U2 switching IC SN6505B, but it is not clear where U2 gets its bias from.   U2 bias and the output of its transformer needs to be up in spec by the time PWMH is ready to switch, which is after a few more cycles of PWML once the input start-up voltage criteria is met (Ivsl_run at the VS input).

5. The components associated with the FB input (C15, R16, R20, Q4(?)) are shown off to the right of the schematic diagram, but should physically be located very close to the IC to minimize susceptibility to induced noise currents in the FB loop with the opto coupler. Tie the opto-emitter back to ICGND at the IC, and keep the loop area as tight as possible.

6. We have updated guidance on the value of R24(?) in series with the CPC3909 source. It is now 121R, but the preferred value is 510R when using GaN MOSFETs.

7. VS resistors R6 and R7 should also be located close to the VS input of the IC to minimize capacitance on the VS node. Stray capacitance adds delay to the Vaux switching edges and too much delay can fool the control into skewing the PWMH on-time tuning in the wrong direction.

8. I see that the U1 UCC24612 controller has its VDD shorted to the REG pin. That’s okay as long as the bias voltage is less than 9.5V, or the REG will be back driven and overstressed .

9. I suggest to add in resistor placeholders, even if only 0ohms, in series with each U1 pin VD, VG and VS, to provide for future flexibility to make adjustments to operation. Rvg can dampen possible ringing between Cgs and any stray L. Rvd can be increased to 100’s or K-ohms to use pin capacitance for a minor turn-on delay if necessary. Rvs can exploit the 150uA bias current out of the VS pin to adjust the turn-off threshold if necessary.  If prototype evaluation proves them unnecessary, you can take them back out, but it’s tough to put them in without space for them.

10. The VCC1 of each isolator driven by the U4 LDO should work okay. I don’t see a problem with it.

Please check these items, especially #1.

Regards,
Ulrich

Hello Robin,

I believe that your observation is on the right track.  If VDD voltage is stuck at a low point, it usually indicates that there is a load on VDD that exceeds the current coming in from the depletion Fet. The bias current of the TPS7A is very low, so I don't think it is the TPS itself loading VDD, but maybe the isolator loads on the output of the TPS7A.

On your earlier concern, the on-resistance of the CPC3909 and of the BSS126 Fets are inconsequential to the charge up current through them.
This is because they (whichever is used) will not be in a saturated-on state, but will be in a "linear" region where the equivalent resistance is much higher (depending on the input voltage ) to match the actual current passing through them (it).

That current level is throttled by the source resistance between the source pin and VDD/HVG.  The Fet becomes a crude current source controlled by its threshold voltage.  Before VDD rises above 1V, there is about 12K internal resistance between SWS and HVG.  Above 1V this resistance drops to ~1K.

During start-up, HVG tracks VDD (not the other way around) and as current builds up through the external Rsws and internal 1K, the voltage drop increases until it reaches the depl-Fet threshold voltage of about -2V or so. Higher current makes it more negative and chokes it off more, and lower current does the opposite, so it settles at a "constant " current to charge VDD to 17.5V.  The difference in the FEts comes down to the difference in their respective thresholds.

Changing Rsws to 510R is a recommendation to help protect the BSS126 from excess negative currents under certain transient conditions.  The BSS126 is not a rugged part. Since GaN Fets have a ~4V body-diode voltage, if ZVS is forced heavily, a lot of body-diode current in the GaN will set up -4V across Rsws and force current reverse through the depl-Fet's body-diode.  Once that is out of the way, the Depl-Fet body diode must reverse recover before substantial drain voltage can be applied.  IF the low-side on-time is very short, Vds will swing high while the depl-Fet is still recovering and may damage it. 510R helps reduce that current. Bu tit can't be much higher because it (along with the internal 1K) will throttle the charging current too much and the VDD may not be able to get up to 17.5V, depending on all of the other loads on VDD beside the UCC28780 itself.  

We don't have experience with the CPC, but since it is "bigger" I think it might be more rugged with respect to the +dv/dt during reverse recovery issue. 
But I can't say for sure.

Regards,
Ulrich