Original question:
Hi TI,
We are having radiated emission issue in both FCC and CE testing with using this charging IC.
We have tried adding common mode chokes for improvement but without much success.
Can help to review the schematics and layout and provide any suggestions for improvement??
The configure are as follow:
15V USB PD input, 1.8A charging for a 3S2P 18650 lithium battery pack.
Charging schematics:
PD input
Layout
PCB 3D
EMC results:
Hi YWM,
The priority for any buck switching converter is to place all input capacitors (PVCC capacitors) as close as possible between the input pin (PVCC) and GND. On this layout, this capacitors use vias to get back to the GND pin. As a test, I suggest scraping some etch and soldering new C145=1nF and C139=100nF decoupling capacitors, in larger footprint, across the top of the charger IC between PVCC and GND, with non-conductive tape over the SW vias. This lower impedance return path may fix the radiated noise issue. If this works, I suggest re-laying out the board to match this concept, by viaing the SW pins down and then back up to the inductor.
Next in placement priority are the REGN and BTST capacitors, C135 and C146. I couldn't find those on the layout. The fewer vias for the those, the better.
Last would be the decoupling output capacitor for SRP, C136, which appears to be nicely placed with low impedance.
As a last resort, you can add an RC snubber from SW node to GND pin and "tune it" to your board layout through empirical measurement (see app note for a boost converter snubber using same concept at 
) and/or add a common mode choke on the input similar to what is shown below in the excerpt from a reference design. The spec for the choke used in the excerpt from the reference design is also attached. TCX1 TC29 T 8X3X4CG X0183400.PDF
Regards,
Jeff
Jeff,
1) Corresponding to your suggestion in 1st paragraph, we are using 4 layer board with L3 as a ground plane.
So we kind of follow evm's layout as shown below with the via to GND?
But yes on the top layer except the via we do not have a short direct connection between the IC's PVCC and IC's GND pin, is this an issue???
L2:
L3 (GND plane):
2) REGN and BTST capacitors, C135 and C146 are located on the other side of the board, would this be a concern?
Thanks~
Jeff F said:Hi YWM,
The priority for any buck switching converter is to place all input capacitors (PVCC capacitors) as close as possible between the input pin (PVCC) and GND. On this layout, this capacitors use vias to get back to the GND pin. As a test, I suggest scraping some etch and soldering new C145=1nF and C139=100nF decoupling capacitors, in larger footprint, across the top of the charger IC between PVCC and GND, with non-conductive tape over the SW vias. This lower impedance return path may fix the radiated noise issue. If this works, I suggest re-laying out the board to match this concept, by viaing the SW pins down and then back up to the inductor.
Next in placement priority are the REGN and BTST capacitors, C135 and C146. I couldn't find those on the layout. The fewer vias for the those, the better.
Last would be the decoupling output capacitor for SRP, C136, which appears to be nicely placed with low impedance.
As a last resort, you can add an RC snubber from SW node to GND pin and "tune it" to your board layout through empirical measurement (see app note for a boost converter snubber using same concept at
) and/or add a common mode choke on the input similar to what is shown below in the excerpt from a reference design. The spec for the choke used in the excerpt from the reference design is also attached. TCX1 TC29 T 8X3X4CG X0183400.PDF
Regards,
Jeff
Jeff,
Given the pin assignment of BQ24172, it seems not feasible to route the ground pin of PVCC decoupling capacitors to IC's ground pad without using vias??
Any suggestions or reference???
Thanks,
YWM
