• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 131 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCD9090A: Customer need UCD9090A internal circuit delay specification

Paul Yeh
Genius 14925 points
Part Number: UCD9090A

Hi Team,

My Customer would like to know the internal circuit delay timing specification for Rail Enable pins?

As we know customer can program Enable power rail ON Delay timing to zero, so does it meant there is no any delay when UCD9090A is power on?

Customer is asking is there any delay when Rail enable issued?

Thanks

I also captured portion communication content with customer before.

  • 0
    TI__Guru 60800 points

    Hello

    The delay and processing is handled by firmware inside the chip therefore there are processing delay always. For example, device polls the  CTRL_PIN state as fast as possible but this varies on the system. when the CTRL_PIN's state is determined, device will try to enable each rail there would be some overhead delay which is about 10us. 

     Does your customer have any specific requirements?

    Regards

    Yihe

  • 0 in reply to yihe
    TI__Guru 60800 points

    Hello

    We haven't heard from you for a while and assumed that the issue has been solved. Please reply if any further help is needed.

    Regards

    Yihe