CSD95496QVM: Need help debugging a specific failure mode related to TSEN/TAO

Hi Jim,

The CSD95496 may pull TAO low if: 1. UVLO protection. Please verify the power up sequence and make sure VDD/EN are high before PWM signal is applied. 2. open pin detected. Power stage will check if LSET/REFIN/VOS pins are floating, and if floating pin detected it will pull TAO low. So you may want to double check if any of those pins are floating or any soldering issue.

It could be pulled low by one of the two power stages, unless you have 0ohm in-series on each TAO signal traces then you can remove one of the 0ohm to see which one caused the issue, otherwise, you may have to unsolder one of the power stage to see if the TAO gets back to normal.

I would recommend to check if VDD voltage is normal and if any open pins (soldering of power stage pins and components connect to those pins) as I mentioned above first. 

Thanks for the quick reply!  I replied via email but it looks like that doesn't make it to this forum.  I am copying my reply below.

I lifted the resistor we have going to the TAO pins and was able to isolate the issue to a specific power stage.  I see no other issues explaining why we are seeing this fall out.  We will replace only the failing power stage and confirm everything runs fine with that power stage swapped out.  If there is any additional info about what else might cause this issue then I would like to hear it.  Thanks for your time!

Hi Jim,

Thanks for the update, and it's good to know that we can isolate the issue to specific one. Did you try to reflow the solder to see if the issue went away? Just want to check if it's related to soldering issue.

Then we may also want to check voltage waveforms on VDD/LSET/IOUT/REFIN/TAO pins during power up (may use VDD rising edge as trigger), the details in waveforms may helps us to understand what might be going on.

The last thing we may want to try might be swapping the device to see if another device would work on this socket. 

Hi JIm,

The PWM signal is generated by controller and it sounds normal that it's in tri-state before EN goes high. And you are correct that it's also normal if TAO is low so controller responded and disabled this power stage. Please check other thoughts in reply below to your questions.

Our production facility doesn't like to reflow parts to see if the issue was a reflow issue.  In this case we are using a QFN so we can visually verify the connectivity to the pins on the perimeter.  That all looks good.  We are swapping out the failing power stages on 4 systems we have the issue with.  Unfortunately that takes a couple weeks to get done in our production facility so I will have to get back with you on the test results.

Parallel to this issue I am learning that we have field returns coming back with this very same issue.  Daniel Carlson with TI is talking to our HW team directly on the field failures also.  This suggests the failures we are seeing in production may be good enough at some point to pass through production testing and eventually fail in the field.  It seems clear that we have factory test escapes for latent failures occurring.  Thus, if there is a known issue that we need to screen for then we need to know ASAP so we can implement the correct screening actions.  Please clarify if there is any known issue that could be tied to what we are seeing.  Thanks, Jim

Hi Jim,

Thanks for the update.

I am not aware of any. BTW, you may want to reach out to TI field support team for further discussion. It may not be appropriate to discuss those topics on public forum.

I have another question for you.  We looked at two of our systems and found that the TAO pin did come up to 0.8V for each power stage as long as the zero ohm resistor used to tie it to the TSEN pin of the controller was removed.  So in this specific case it seems clear that the TSEN pin is causing the TAO pins to be 0V when connected via their 0-ohm resistors to the TAO pins of the power stages.  My understanding is that TSEN is just an input pin.   We see 40 ohms to ground on this pin in a non-powered state so it is not a dead short to gnd.  Is there a known failure mode where the controller might drive the TSEN pin Low?

Hi Jim,

I will try to find someone familiar with the controller to help with your questions.

TPS53622 should not pull the TSEN pins low, unless it's not being powered by 3.3V. Can you compare your ohm-measurement of TSEN to a normal board? It sounds like to me like that controller could be damaged. 

The controller is getting power because we are able to read the status registers via software.  We are having the controller replaced on both of these systems so well see if that resolves the issue.  Thanks for the quick feedback!

Hi Jim,

Please let us know if you have any update.

Will do.  Unfortunately it take the production facility a couple weeks to get this type of part swap done so it may be a while before I get back with you.  Thanks again for the support!  

Hi Jim,

Understood and well noted. We can revisit this post few weeks later.

I have one more question I wanted to run by you.  Our design does not populate the pull-down resistor on the TSEN net.  The data sheet shows this pull down populated in the 2+0 design implementation.  Help me understand if this is a concern.  I populated the resistor on one blade where the issue turned out to be a power stage and it did not have any affect.  That said, we came across 2 other blades where the power stages did not seem to be the issue and we are in the process of replacing the controller.  I never checked to see if adding a pull down on the TSEN pin would have made a difference on those systems.  Could those 2 systems be seeing this issue because we don't have an external pull-down on the TSEN pin?

This resistor just provides some loading on the TSNS pins to ensure they do not float up due to leakage, since the power stage intentionally do not sink current into their TSEN pins during normal (e.g. not fault or UVLO) operation where TAO is not being driven high/low, but following the temperature. I cannot see how this would lead to hard failures in any case. Worst case, you could see over temperature faults if you had excess leakage on the TSEN pin.  

Thanks Matt,  What about prior to soft start?  Could leakage current without a pull down allow the voltage on the TSEN pin to float above the 150mV level and cause the TSNS_LOW to assert because TSEN>=150mV before soft start?

TSNS low is a hysteretic fault for the controller. If you assert VR_EN before the TSNS pin is out of TAO LOW, it will basically just wait for it to go high, then start switching automatically when it does. There is a small nuance that it should not set the status but for TSNS low if this occurs, only at the first enable edge after POR. This is to enable power sequences which do not have 3.3V coming before 5V. 

All of that to say, as long as the powerstage can drive TSNS above the threshold when its powered (assuming of course the controller is not broken and TSNS pin low impedance), that condition would not block power conversion from starting. 

Got it.  Much appeciated!