This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS56C230: Expected problem with Cout voltage derating

Part Number: TPS56C230

Hi team,

For 5.0V output with TPS56C230, the customer is using 4*47uF (10V rating) + 1*10uF (16V rating) + 1*100nF (10V rating) + 1*1nF (50V rating).

When it comes to 47uF capacitors, I expect its capacitance would decrease by half due to the voltage derating. Even though I consider the derating, the total output capacitance value meets the Cout.min requirement. In this case, do you expect any other problem with the capacitor derating ?

  • Hi Ella,

    If the capacitance after degrading can satisfy our recommended capacitance range, there will be no concern for stability.

    Just need to make sure that the load transient performance and ripple could meet customer's target, since the smaller capacitance after degrading could cause both worse load transient and ripple performance.

    You could use our online Webench model to complete the simulation if there's a demand.

    Thanks,

    Andrew