TPS65911: TPS65911AA2NMAT No voltage at output

Correction made, BOOT1 (Pin J5) = HIGH, EEPROM mode. As TPS65911AA2NMAT is dedicated for K2G12 Soc chip.

Should PWRON (Pin E4) connect to permanently HIGH for PMIC output enable?

Please suggest.

Thanks

Hi, Anand,

  My EVM test shows a falling edge of PWRON can power on the device; but I don't get all rails on as its user guide descried. Would you please try that and let's know if it works for you? 

Thanks!

Phil

Hi

Unfortunately, I don't have access to PWRON and PWRHOLD pins in PCB layout circuit. They left unconnected in PCB layout as recommended in EVM.

Why should faling edge needs to be provided manually through switch? There is no external master in my design to control ON/OFF of PWRON pin. Expectation is power sequencing needs to be initiated when all input voltage are available to PMIC.

I have EVM board Rev D  version (EVMK2GXS) for cross reference and testing.

My current Board failure state as, VTRC = 1.8V, VREF(Pin G8) = 0V, All SMPS and LDO outputs are OFF.

My Additional observations are as follows,

1) PWRDN Pin

         - Connected to LOW in the EVM as default. From SWCU187A understood that, PWRDN pin configured as Active HIGH for TPS65911A. My design changed to make PWRDN to Pull LOW (GND). But there is no change, PMIC still in disable mode.

         - In EVM,  PWRDN pin pulled to HIGH and checked for observation. It gave results, VRTC=1.8V, VREF (Pin G8) = 0V All SMPS and LDO's OFF. Which is as same as my board current failure state.

         - In EVM, PWRDN pin pulled to LOW, gives VRTC = 1.8V, VREF = 0.85V and All SMPS and LDO's are ON.

As per Specification sheet, VREF=0.85V for Active and SLEEP state; VREF=0V for OFF state.

In My circuit, changing PWRDN to HIGH or LOW, there is no change in PMIC outputs state. All output OFF.

2) PWRON

      - In EVM, PWRON Left unconnected. Through there is reset switch provision available for creating rising and falling edge, without pressing reset switch PMIC gives output. Also SWCU187 clearly shows, initial power sequencing not depends on rising / falling edge of PWRON signal.

In my design, left this pin unconnected and no access for testing. there is no trace, via connected to this BGA pin. But this state is as same as EVM. But PMIC not giving output voltages in my design.

3) BOOT1

     - In EVM, BOOT1 connected to HIGH (VRTC). Logic LOW= Fixed Boot; HIGH= EEPROM boot. Both EVM and my circuit design are tied to HIGH state (VRTC).

4) SLEEP (Pin F1)

      - In EVM, SLEEP pin connected to Processor GPIO. In my design, it is pulled to +3.3V using 10 resistor, as no plan of keeping PMIC in Sleep mode.

      - With 10k pull up tied to 3.3V, it was observed 0.8V at SLEEP pin.

       - With 1.5k pull up tied to 3.3V, it was observed 1.66V at SLEEP pin.

             Above voltages are steady and constant. Not sure, Why PMIC sinking so much current. Specification datasheet says, SLEEP pin can sink maximum 10uA when active.

5) External Oscillator

Per SWCU187U, EEPROM configured to use Internal RC oscillator. Hence in my design I have not used external crystal oscillator. Same validated with EVM board by removing crystal from the board. EVM PMIC works fine without external crystal oscillator.

6) PMIC part Marking in EVM

      - I am using TI EVM ReV D (EVMK2GXS) board for reference and testing. The part marking on the PMIC chip used in EVM is TPS659114A2 (which is meant for iMX6 processor) instead of TPS65911A (which is meant for K2G12 processor). Not sure, why EVM using wrong PMIC part number. But it is doing its job same as TPS65911A. I am using PMIC TPS6511AA2NMAT for 66AK2G12 processor.

• Is EVM PMIC TPS659114A2 loaded with EEPROM configuration file dedicated to 66AK2G12 Processor? Is that reason, not seeing problem with wrong PMIC part in EVM?
• Is TPS6511AA2NMAT loaded with EEPROM config file dedicated to 66AK2G12 processor power sequencing at factory before shipping? Looking at the current performance, I am suspecting whether this part not loaded any configuration file inside? How to validate this?

The circuit design is as similar to EVM design, Why PMIC in OFF state? How to make Active?

Would like to have telephonic conversation or Meeting to discuss details. Any other suggestions welcome.

Thanks

Anand

Hi, Anand,

  By further investigation, we did find the issue with TPS6511AA2NMAT that EEPROM config file dedicated to 66AK2G12 processor power sequencing may not be programmed properly at factory before shipping. 

  The team is still working on locating the root cause and a solution to provide customer a fix.

   I'll keep you updated as soon as we have solution. 

Thanks!
Phil