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UCC2806M: Setup to disable current limit, and operate at 50% duty

Darren (FAE)
Expert 5483 points
Part Number: UCC2806M
Other Parts Discussed in Thread: UCC2806, UC2846, UC3846

Planning to use the device in 50% duty-cycle, with a setup shown in the attached pdf.
NI,INV pins are set for 50% duty.

Considering pulling CURLIM and COMP pins to VREF via resistor to disable current limit.

[Questions]

[1]
Is the setup shown in the attached file acceptable for holding 50% duty while disabling current limit?

[2]
Not sure how the Transistor between Error Amplifier (EA) and CURLIM  works...?
When EA output is MAX, does the transistor turn on, and current limit operation happens...?

 

ucc2806_pin connection_210416.pdf

  • 0
    TI__Mastermind 24525 points

    Darren,

    Pulling CURLIM above 350mV will latch the PWM OFF until CURLIM is released. This is regardless of the state of COMP so this means the PWM output are 0, not 50% as you expect. I believe the internal PNP is discharging COMP during the CURLIM event so that the PWM can restart once CURLIM is released. You can have a condition that causes EA max but still be less than 350mV on CURLIM. You can imagine from steady state operation, slowly decreasing VIN below the designed minimum VIN, duty cycle will go to max, current limit may still be ok then output voltage regulation begins to drop.

    Regards,

    Steve M

  • 0 in reply to Steven Mappus1
    TI__Expert 5483 points

    Hi Steve,

    Your reply above resolved my question, but I have a follow-up.

    I understand the actual current limiting happens based only on CURLIM voltage.

    I can see on the Block Diagram how CURLIM above 350mV results in current limiting, and PWM OFF.

    But I am having trouble seeing from the Block Diagram how the current value measured at CS+/- and CURLIM are related.

    Could you help clarify for me?

  • +1 in reply to Darren (FAE)
    TI__Mastermind 24525 points

    Darren,

    CURLIM is used to set the current limit threshold and the behavior (latched vs non-latched) that should be taken when over current condition exists. I believe CURLIM is intended to be a second level overcurrent protection (OCP). CS+/- is a differential current sense used for current mode control.

    Steve M

  • 0 in reply to Steven Mappus1
    TI__Expert 5483 points

    Hi Steve,

    [1]
    I understand that CS- is tied to GND, and CS+ is tied to a point between the N-CH MOSFETs SOURCE and a sense resistor to GND. 
    When AOUT and BOUT are working, current flows through this sense resistor to GND, creating a voltage drop, and increasing CS+ in relation to CS-.

    [2]
    This voltage drop is multiplied by the 3x gain stage (between CS± pins on p8), and gets fed into a Comparator, with a threshold set to 0.5V less than the output of the EA section (and some current sources, PNP transistor, etc...)

    [3]
    The output of the comparator goes into an SR latch stage, triggering the overcurrent condition.
    How is this overcurrent detection threshold value set? There is no simple DS equation for calculating external components to set CS+/- threshold limit?

    [4]
    Furthermore, there is no part of the block diagram showing how the threshold limit set by the CURLIM voltage divider to VREF, and this output from the CS+/- stage, relate.

    How do they relate?

    [5]
    I sort of understand that CS+/- initially triggers the overcurrent detection event, which initiates the 200uA internal pulldown source on CURLIM, and if the voltage at CURLIM is >350mV, the device stays latched off.

    But the DS only gives an equation for setting the latch-off threshold, or release threshold,  and since it is a 200uA pulldown through a voltage divider connected to a stable 5.1VREF, I don't see how the threshold at CURLIM can change...

    Can you please help clarify as detailed as possible, how the CS+/- current-limit threshold is set, and how the CURLIM is used to keep the device in latchoff (aka the mechanism that the >350mV goes to <350mV)

    Thanks,

    Darren

  • 0 in reply to Darren (FAE)
    TI__Mastermind 24525 points

    Hi Darren,

    The data sheet and block diagram are not clear on the relationship between CURLIM and CS+/- and I agree the block diagrams often do not show the level of detail needed by some customers. From the guidance provided in the UCC2806 data sheet and supporting app notes, the answers I've given are the best I can provide. Since UCC2846 is a BiCMOS version of UC2846, you can check the UC2846 data sheet and product folder for more info. UC2846 also includes a SPICE model you can try. U-93 is a UC3846 app note introducing the function of CS+/- and CURLIM.

    Steve