I have currently designed using ucc5390 an h bridge. here are the schematics and file.
i am confused about gate resistance value.
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I have currently designed using ucc5390 an h bridge. here are the schematics and file.
i am confused about gate resistance value.
Hi Mohammad,
1. I reviewed the schematic and your design is very robust. You might be taking too many precautions, actually.
a. Zener clamps can be regular diode clamps, just with VDD2 clamp from OUT to VDD2. Your circuit will work, but I’ve seen this more commonly in other systems. It also eliminates some of the Zener leakage current.
b. Gate resistors are sized far bigger than needed. They add more parasitic inductance to your circuit which reduces switching performance. You would probably be able to use one 0805 turn on, and one 0805 turn off resistor. These resistors normally can handle much larger peak current, and should be okay as long as you do not violate their Pdis rating. An example of how to calculate this Pdis is in the datasheet, section 11.2.2. Just change out the internal resistance with the external resistance to ensure it does not overheat.
c. These caps can be reduced to 10uF ceramics for your current gate charge requirements. Ceramic capacitors can sustain very high peak currents, and most of the peak current will already be supplied by the 100nF caps located close to the IC. 180uF is far too much for almost any gate driver circuit using traditional switches. Also the Zener diodes are unnecessary since you’re already using LDOs to regulate these rail voltages.
d. Add filter capacitors to inputs. Values can be determined using calculations from the datasheet section 11.2.2.1
e. Freewheeling diodes are unnecessary since FETs have body diodes.
2. One supply should be fine to power all 4 Vcc1 since they are referenced to the same ground.
3. Using the same VCC1 rail to power the 4 isolated dc-dc converters should be fine, assuming the VCC1 rail can source enough current to power all of these devices.
4. If you use all ceramic capacitors, these have very low ESR. Their limiting factor is actually ESL, which slows down the possible di/dt of the driver. Ceramics with X5R or X7R dielectric will provide the best performance for our drivers. Please see figure 3 in this application note to see difference in impedance between different capacitor types and packages.
http://www.ti.com/lit/an/slyt639/slyt639.pdf
If this helped answer your question, could you please press the green button?
Thanks and best regards,
John