During the transition from LPM to ABM, the Vds surge of the synchronous rectifying FET jumped up.
I think that the operation is as described in (1) to (4) in the attached file, but is it correct?
Also, what determines the time of ① + ② (ON time of high side FET when shifting from LPM to ABM)?
I would like to shorten the time of ① + ② and suppress the surge of the synchronous rectifier FET (point A in the attached file). Is there any adjustment method, countermeasure circuit, etc.?
Also, for the surge at point B in the attached file, we are considering countermeasures in the direction of using a synchronous rectifier IC with a short minimum ON time, but are there any other possible countermeasures?2148.waveform.pdf