This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
We are creating the library part models for the 66AK2H14 CPU from TI and need to know if this part requires pin-package length compensation for the footprint (AAW1517B package). Normally we get this data for parts like these so the layout team can account for the package propagation delay on critical interfaces (like DRAM). Can you please let me know if this is required for this part?
Thanks,
Adam
Adam,
There is no need to consider internal package skew. You should follow this appnote for DDR layout/design guidelines, which states the maximum amount of skew that should be met on a customer PCB:
DDR3 Design Requirements for KeyStone Devices (Rev. C)
Regards,
Kyle