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66AK2H14: DDR3 Output Clock and PTV compensation

Anthony Diak
Intellectual 430 points
Part Number: 66AK2H14

I am debugging a custom designed board, and am having issues configuring the DDR3 (both A and B).


Our DDR3 design is heavily based upon the EVM, and I am running the GEL script from the EVM (modified slightly for the memory chips we selected).  I am not seeing a clock output after configuring the PLL.  I have double checked the configuration of the PLL and used the Keystone DDR3 debug GEL script to verify the configuration.

I have searched on the forum and found this post talking about DDR3 issues.  The poster identified a resistor mismatch (RR1) going to the PTV compensation pins (DDR3ARZQ0-2 or DDR3BRZQ0-2) .  I took a look at our schematic and we missed these pins (they are floating).  We are going to have to re-spin, but want to try and debug as much as possible before doing so.

Here are my questions:

  • Do the DDR3 output clocks (DDR3ACLKOUTP/N0 and DDR3BCLKOUTP/N0) depend on the PTV compensation pins (DDR3ARZQ0-2 or DDR3BRZQ0-2) to even output a clock?  I see nothing when I probe the pins, before and after PLL configuration.
  • Is there any work-around configuration possible to leave these not connected but get the DDR3 up and running, so I can verify any more of the design before we re-spin?

  • 0
    TI__Guru 65405 points
    Hi Anthony,

    I've forwarded this to the design team. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Guru**** 161600 points

    Hi Anthony,

    Is there any work-around configuration possible to leave these not connected but get the DDR3 up and running, so I can verify any more of the design before we re-spin?


    You should align with the Data Manual recommendations and add those resistors. See DDR3 Design Requirements document (www.ti.com/.../sprabi1b.pdf), Section 4.5.2 Routing Impedances – KeyStone II Devices:

    "During writes, the output impedance of the KeyStone II device is approximately 40 Ohm. It is recommended that the SDRAM be implemented with a 240 Ohm RZQ resistor and be configured to present an ODT of RZQ/6 for an effective termination of 60 Ohm"

    As for your first question. You should be able to get the clock out of the Keystone SoC. Check the DDR3 Initialization document, Section 3.2 KICK Unlock and DDR3 PLL Configuration, make sure you comply with the following requirement:
    "The KICK register unlock and DDR3 PLL configuration code may reside elsewhere in the initialization code but they must be completed prior to initializing the DDR3 controller and SDRAM. Prior to writing to the DDR3 PLL configuration registers, the KICK registers need to be unlocked.
    Example 2 shows the unlocking of the KICK registers. Once the KICK registers have been unlocked, the DDR3 PLL configuration can be completed."

    Hope this helps.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 430 points
    Yeah, we need to add the resistors -- they just got missed somehow in our design.

    As for the clock, I believe I have followed the correct KICK unlock sequence, as I am using the GEL script from the EVM. The script works on the EVM (I see the clock and the DDR3 works). So you are saying the missing resistors should not stop the clock from coming out? Would anything else cause the clock to not output? We have verified the 100Mhz input clock (same as EVM design) is coming in, and the PLL is supposedly configured.
  • 0 in reply to Anthony Diak
    TI__Mastermind 46460 points

    Anthony,

    The output buffers in the DDR are impedance compensated.  This compensation is based on the current through the PTV resistor.  The outputs are completely non-functional without that resistor installed.  That includes the DDRCLKOUT pins.  A resistor is needed to do any further functional testing of the DDR interface.  Can you have a hole drilled under the ball and a wire attached?  I have heard of this being done in extreme cases such as this.  You would have to discuss this with your PCB assembler.  We have no expertise with this process.

    Tom