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AM5729: RTOS PCIe Example code read issue

Rajesh War
Intellectual 525 points
Part Number: AM5729

Hi,

We are trying to test our custom board with TI provided PCIe example code. 

Here Cyclone V FPGA configured as endpoint and TI AM5729 processor configured as Root Complex.

Outbound - TI processor configured as Root complex and able to write/read in to/from Cyclone V FPGA .

Inbound - TI processor configured as Root Complex and FPGA able to write into TI processor. But facing issue when FPGA reading back from TI processor.

Could you please help us to know whether we need to do any modification in PCIe example code to enable Read operation in Inbound communication.

Package : pdk_am57xx_1_0_17

Processor : AM5729

Board : Custom board

OS : RTOS

Attached signal tap result of FPGA read operation

.

Regards,

Rajeshwar

  • 0
    TI__Expert 6870 points

    Hi,

    Rajesh War said:
    We are trying to test our custom board with TI provided PCIe example code. 

    Can you mention which example you are referring to?

    Rajesh War said:
    Inbound - TI processor configured as Root Complex and FPGA able to write into TI processor. But facing issue when FPGA reading back from TI processor.

    As you mentioned that outbound is working fine and also write is happening during inbound configuration, it may be a configuration issue. Please provide the path of example you are trying.

  • 0 in reply to ANUBHAV AKASH
    Intellectual 525 points

    Hi,

    This is the path of example code which we are using for testing.

    C:\ti\pdk_am57xx_1_0_17\packages\MyExampleProjects\PCIE_idkAM572x_wSoCFile_armExampleProject
  • 0 in reply to Rajesh War
    TI__Expert 6870 points

    Hi,

    The driver example is validated with use case mentioned in the documentation, i.e. AM572x as RC and AM572x as EP. If you are using some other Hardware then the same configuration might not work. Examples are there to validate the SOCs usecase.

    You have to configure the Inbound translation logic according to Cyclone V FPGA.

    Moreover, is the link coming up?

  • 0 in reply to ANUBHAV AKASH
    Intellectual 525 points

    Hi,

    Yes, link is coming up and cyclone V fpga able to write into AM5729. 

    We have read "Only incremental bursts (INCR) are supported by the PCIe controller master port." in TRM manual. Is it conveying that only burst mode is supported by processor when processor is in RC inbound mode?

    Now FPGA can write and read it from processor in burst mode. when we are trying to check the data written into processor in memory view(CCS), nothing has written in that location. We made our buffer to be volatile as well as disabled cache for that buffer. Still issue persist. 

    We have configured  the Inbound translation logic according to Cyclone V FPGA.

  • 0 in reply to Rajesh War
    TI__Expert 6870 points

    Hi,

    Rajesh War said:
    "Only incremental bursts (INCR) are supported by the PCIe controller master port."

    please see the NOTE before section 24.9.4.4 in TRM.

    Also, go through section 24.9.5.2 of TRM for detailed initialization sequence.