AM4376: EMU0 signal goes to low at start up under high temperature

Hi Koichiro,

Are you able to confirm if the SoC is held in reset by monitoring the PORz signal? If it is low the SoC is held in reset, so it should be high.

Given that you can read the 0x30000 address I assume the device is not in reset.

Are you able to read the Tj, thermal junction temperature, of the AM335x device before and during failures?

If you are unfamiliar with the process, this thread discusses the method:

https://e2e.ti.com/support/legacy_forums/embedded/linux/f/linux-forum-read-only/412730/am335x--how-to-enable-soc-die-temperature-sensor-on-sdk8-0

Regards,
Colin

Colin,

The device is AM437x, not AM335x.

The PORz signal is released, but Program Counter(PC) does not proceed due to Wait-in-Reset.
So no boot process is started.
Please see TRM Section 31.1.3.2.

Then customer connected CCS and confirmed PC is still at reset vector (0x30000).
At that moment, Wait-in-Reset is released by CCS, so if code is "run" from CCS, boot process is started normally.

My question is why EMU0 pin goes to low at 50C even the signal is pull-up.

Thanks and regards,
Koichiro Tashiro

HI Koichiro,

Thanks for the friendly reminder and for the additional clarification.

Does the customer have 4.7kOhm external pullups to VDDSHV3 on EMU0 and EMU1 pins? Both these pins must be high at reset release time, otherwise the device may enter the "wait-in-reset" state.

Regards,

Colin

Hi Colin,

Colin Callaghan said:

Does the customer have 4.7kOhm external pullups to VDDSHV3 on EMU0 and EMU1 pins?

Yes. Both signals are pull-up with 4.7kOhm to VDDSHV3 (IO 3.3V in waveforms).
EMU1 is pull-up properly. Only EMU0 shows strange behavior.
Please see below waveforms (Left: EMU1, Right: EMU0).


And such behavior is observed on specific two boards under ~50C temp.

Thanks and regards,
Koichiro Tashiro

Hi Colin,

Do you have any idea about this behavior?
Is this device failure?

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

When does the customer ramp the 1.8V VDDS supply relative to VDD_CORE and 3.3V VDDSHV3 supplies? 

VDDS is the bias supply for all dual voltage IOs and must be ramped before IO supplies.

Regards,

Colin

Hi Colin,

Please see power up sequence below:

VL1_8V and V1_8D_AM437X are 1.8V power supplies to AM437x.
VDC1_1_1V is VDD_CORE.
VDC4_3_3V is 3.3V VDDSHVx

Power up sequence seems correct.

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

May I ask for a copy of the JTAG schematic?

How many devices is this observed on? If it is just one, has the customer conducted an A-B-A swap?

Regards,

Colin

Hi Colin,

I will send you the schematic in separate e-mail.

Colin Callaghan said:

How many devices is this observed on? If it is just one, has the customer conducted an A-B-A swap?

I asked customer to check these points.

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

We are still looking into this with the Design Experts. I am pinging them again now.

Regards,

Colin

Hi Koichiro,

This issue is also observed on Maxwell devices. The known workaround on Maxwell is to decrease the supply ramp below 1ms. What is the ramp time that the customer observes?

Regards,

Colin

Hi Colin,

Colin Callaghan said:

What is the ramp time that the customer observes?

Which supply rail are you asking for?
As you can see some waveforms I already sent;
- VDD_MPU ramp time is ~1.6ms
- VDD_CORE ramp time is ~1.6ms
- IO 3.3V ramp time is ~3.2ms
- 1.8V ramp time is ~0.3ms

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

not sure why I just saw your response today. I sincerely apologize for the late response this time.

I quickly forwarded your response to the Design Experts. I predict they will say either VDD_CORE / VDD_MPU should be under 1ms, but let me wait for them to confirm that before you communicate that to the customer.

Lastly I admit I had difficulty seeing the time-scale (ms/div) on the oscilloscope image that you shared on this thread. Could you please confirm the time-scale?

Regards,

Colin 

Hi Colin,

You can see the time-scale here (RED circle). In this waveform, it is 1.6msec.

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

The Design Experts confirmed the IO 3.3V ramp time should be under 1ms, and it is currently 3.2ms.

Can the customer reduce this ramp time? The Design Experts believe this is the issue.

Regards,

Colin 

Hi Colin,

Customer tried to reduce IO 3.3V ramp time. Now it is ~240us, but the issue still occurs.
Please see below waveform with modified IO 3.3V ramp time.
EMU0 signal is once goes up to 3.3V, but soon goes down around 500mV.

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

The Design experts are convinced that something is pulling the EMU0 IO low since the only external connection to the pin is a 4.7k pull-up. Are we certain that there is nothing pulling the signal low anywhere in the signal chain?

Regards,

Colin

Hi Colin,

As you can see the schematics I sent offline, there is only JTAG connector to the signal.
And JTAG cable is removed when the issue happens.
So we are pretty sure nothing is pulling the EMU0 low externally.

BWT, what was the mechanism causing similar issue on Maxwell devices?
Is this triggered by only IO 3.3V ramp time?
Is there any chance other factor triggers the same issue on AM437x under high temp.?

Thanks and regards,
Koichiro Tashiro

Hi Koichiro,

The Maxwell Apps team is investigating an issue that may or may not be related, and after it is resolved we can collaborate with them. There is not an ETA for when that will be completed.

Can you reproduce the issue on a TI EVM? If so we can try to replicate it in our local labs. Otherwise we are struggling to debug this issue given the circumstances.

Regards,

Colin