Hi Expert,
I read the Application Report, SPRAC23A–March 2016–Revised November 2017, DSS BT656 Workaround for TDA2x.
2.1.4 Interfacing DSS With the ADV7343 Encoder in Interlaced Mode
For the interlaced display, VSYNC typically is expected to toggle at the start of the line for the even field display and for the odd field, it is expected to toggle in the middle of the line. DSS always outputs VSYNC aligned with the HSYNC, so it cannot generate VSYNC at the middle of the line.
Due to this issue, HSYNC and FID signal outputs from DSS are used to interface with the ADV7343 encoder.
a. The ADV7393 in the report is also an Interlaced Mode?
b. Is the DSS configuration of TDA2x for ADV7393 and ADV7343 the same?
c. Will the sync of RGB565 and RGB888 have the same issue?
d. If I want to use RGB Interlaced output on LCD1, how do I choose Video Encoder?
Could you please give some suggestions here?
Thanks in advance.