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Original question:

AM6548: Wrong ICSSG2 PRU clock speed, when booting from sd-card

AM6442: How to check and modify the ICSSG1 PRU0 frequency under CCS debug?

xixiguohx
Intellectual 720 points
Part Number: AM6442

I'm using a customized board based on Am6442.

I want to use ICSSG1 PRU0. Now I'm using CCS to debug it. I want to check the ICSSG1 PRU0 frequency.

But I can not find any configuration in the ccs_base\emulation\gel\AM64x\Am64x.gel that I used.

How can I check the ICSSG1 PRU1 frequency and config it?

  • 0
    TI__Guru** 100740 points

    Hello,

    Where does the PRU clock come from?

    For information about how AM64x PRU clocks are connected to the rest of the processor, reference TRM sections "PRU_ICSSG Integration" and "PRU_ICSSG Power and Clock Management", and table "PRU_ICSSG Clocks"

    The actual CORE_CLOCK that is used within an ICSSG is selected from either ICSSGn_CORE_CLK (200MHz, 225MHz, 250MHz, 300MHz, 333MHz) or ICSSGn_ICLK (250MHz, synchronized to interface clock). Select with register bit ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN.

    ICSSGn_CORE_CLK is selected from MAIN_PLL2_HSDIV0_CLKOUT (225MHz, 300MHz. PER1 PLL) or MAIN_PLL0_HSDIV9_CLKOUT (200MHz, 250MHz, 333MHz. MAIN PLL). CTRLMMR_ICSSGx_CLKSEL[0] CORE_CLKSEL selects which system clock is used.

    Where are the clocks configured?

    ccs_base\emulation\gel\AM64x\AM64x.gel --> OnTargetConnect() -->runs Set_All_PLL_OFC1(). Set_All_PLL_OFC1() is defined in ccs_base\emulation\gel\AM64x\AM64_PLL\AM64x_PLL_OFC1.gel.

    Set_All_PLL_OFC1() runs Setup(), which is defined in ccs_base\emulation\gel\AM64x\AM64_PLL\AM64x_PLL.gel. Setup() calls Program_PLL(). Since Clocking_Scheme = OFC1, then MAIN_PLL2_HSDIV0_CLKOUT divider is set by MAIN_PLL2_OFC1_HSDIV0_DIV_VAL, and MAIN_PLL0_HSDIV9_CLKOUT divider is set by MAIN_PLL0_OFC1_HSDIV9_DIV_VAL.

    If we check ccs_base\emulation\gel\AM64x\AM64_PLL\25MHz_HFOSC\AM64x_PLL_PARAMS_OFC1.gel, we see that
    MAIN_PLL2_OFC1_HSDIV0_DIV_VAL = 5 (Divide by 6)
    MAIN_PLL0_OFC1_HSDIV9_DIV_VAL = 2 (divide by 3)

    The comments in AM64x_PLL_PARAMS_OFC1.gel make it look like 225MHz is selected for PLL2, HSDIV0, but I think that is a typo. 1800MHz divided by 6 should give 300MHz output unless HSDIV0 behaves differently from the other clock outputs. PLL0, HSDIV9 should be 1GHz / 3 = 333.3 MHz.

    Summary 

    You should be able to read CTRLMMR_ICSSGx_CLKSEL[0] CORE_CLKSEL to see which core clock is being used. If you are initializing the PLLs from CCS, you should be able to adjust the frequencies of the PLL outputs by adjusting the associated values in ccs_base\emulation\gel\AM64x\AM64_PLL\25MHz_HFOSC\AM64x_PLL_PARAMS_OFC1.gel.

    I have not tested the above statements, so let me know if anything needs to be corrected. I will reassign this thread to another team member to double check my work and comment on the PLL2, HSDIV0 question. Please ping the thread in a day or so if they have not responded.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Mastermind 29338 points

    Hi,

    The information provided by Nick is correct.

    The settings for the clock muxes shown in the TRM ICSSG1 integration diagram are configured via these registers:

    ICSSG1, CTRLMMR_ICSSG1_CLKSEL   :  4300 8044h

    ICSSG1, ICSSG_CORE_SYNC_REG     :  300A 603Ch

    These registers can be observed or modified in a CCS Memory Window.

    A GEL script is provided for checking the PLL configurations. The script can be executed from R5F0_0 or DMSC. To execute the script, connect to the desired core and execute: Scripts->PLL Configuration->Get PLL Configurations->Get_All_PLL_Configurations. The output from the GEL script can be used to calculate the PLL output frequencies. Please see the TRM table PLLTS16FFCLAFRACF Output Clocks for details on how the PLL output frequencies are calculated.

    When launching CCS and connecting to DMSC, the DMSC GEL scripts are executed. In this case, the PLL and divider settings are determined by the settings in AM64x_PLL_PARAMS_OFC1.gel, and the settings can be modified in the GEL file.

    The ICSSG1 Core Clock frequency is configured for 300 MHz:

    From CCS Memory Window:

    0x40308044 = 0x00000000 => ICSSG1_CORE_CLK

    0x300a603c = 0x00000000 => MAIN_PLL2_HSDIV0_CLKOUT

    From Get_All_PLL_Configurations GEL script:

    MAIN_Cortex_R5_0_0: GEL Output: Base address: 0x00680000
    MAIN_Cortex_R5_0_0: GEL Output: PLL index: 0x00000002
    MAIN_Cortex_R5_0_0: GEL Output: PLL index register base: 0x00002000
    MAIN_Cortex_R5_0_0: GEL Output: Register: 0x00000020
    MAIN_Cortex_R5_0_0: GEL Output: Reference Divider is:     1
    MAIN_Cortex_R5_0_0: GEL Output: Feedback Divider is:      72
    MAIN_Cortex_R5_0_0: GEL Output: Fractional Multiplier is: 0
    MAIN_Cortex_R5_0_0: GEL Output: Output Divider #1 is:     1
    MAIN_Cortex_R5_0_0: GEL Output: Output Divider #2 is:     1
    MAIN_Cortex_R5_0_0: GEL Output: Number of hsdivs: 10
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #0's divider value is: 6
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #0's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #1's divider value is: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #1's clkout_en: 0
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #2's divider value is: 9
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #2's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #3's divider value is: 6
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #3's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #4's divider value is: 18
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #4's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #5's divider value is: 8
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #5's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #6's divider value is: 8
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #6's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #7's divider value is: 18
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #7's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #8's divider value is: 1
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #8's clkout_en: 0
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #9's divider value is: 5
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #9's clkout_en: 1
    MAIN_Cortex_R5_0_0: GEL Output: Parsed PLL configuration information.

    OSC: 25 MHz

    FOUTP = (25e6/1) * (72 + 0) / (1*1) = 1.8e9

    FOUTPOSTDIV = 1.8e9/6 = 300e6, 300 MHz

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Intellectual 720 points

    Hi Nick and Frank,

    Thank you for your comments, I will try my side to modify it.

  • 0 in reply to xixiguohx
    Prodigy 20 points

    Hi, Frank, I'm also working on AM64x, my question is HSDIV seems wrong according to TRM's formula to add 1 to calculate HSDIV_CLKOUT. So would you help to check the example for 300MHz output, HSDIV value should be 5 or 6? Thanks!

    By the way, we'd like to extract the clock signal on observance pin to verify its actual running speed. but there's a problem to modify CTRLMMR_OBSCLK0_CTRL register, though it's shown as R/W, is there any sequence to activate this output function? Thanks in advance!

    BR.

    Jiaxiang Zheng

  • 0 in reply to Zheng Jacob
    TI__Guru** 100740 points

    Hello Jiaxiang Zheng,

    Please create a new thread for each new question. That ensures that we assign the right TI engineer to look at your post, and helps us make sure that your question actually gets answered. (for example, Frank considers this thread answered because  said he would try it out and hasn't asked follow-up questions. So Frank might never even see your different question here).

    Hello ,

    I moved your question about setting PRU clock frequencies from Linux to a new thread. Please let us know on this thread if you have any followup on setting PRU clock frequencies from CCS. Also, take a look at the FAQ we are working on based on your question and let us know if you have any feedback to make it better: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1041347/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-ccs


    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 720 points

    Hi Nick,

    JiaXiang is my colleague, and we found that the "HSDIV #0's divider value" got from Get_All_PLL_Configurations GEL script has already added 1. And we can connect the R5 CORE in CCS, and then modify the LOCK KICK register and CTRLMMR_OBSCLK0_CTRL register. 

    But still don't know how to configure the ICSSG1 PRU0 frequency in kernel dts file.

  • 0 in reply to xixiguohx
    TI__Guru** 100740 points

    Sounds good, thank you for clarifying.

    Divider Values

    That is correct. If the GEL file
    ccs_base\emulation\gel\AM64x\AM64_PLL\25MHz_HFOSC\AM64x_PLL_PARAMS_OFC1.gel
    says
    MAIN_PLL2_OFC1_HSDIV0_DIV_VAL = 5 (Divide by 6)

    then we expect the GEL script
    Get_All_PLL_Configurations
    to output
    MAIN_Cortex_R5_0_0: GEL Output: HSDIV #0's divider value is: 6

    Modifying CTRLMMR registers 

    You need to unlock the register first. Please reference https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1041347/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-ccs/3851177#3851177 , section "How do I select a different clock source?" for an example of how to unlock using a script in CCS.

    Modify PRU Clock Frequency from Linux

    We will address the "changing the PRU frequency from Linux" question at https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1048998/re-am6442-how-to-check-and-set-the-pru-core-frequency-in-linux

    Regards,

    Nick