Since thread [How to accele access for externalmamory access] is closed, I raise additional question.
[From previous thread]
> Dear Andrel,
>Current read operations are around 10 clocks. But there are 40 or more clock cycles to nextread operations.
> My request is to shrink 40 or more clock cycles interval between read operations.
> I found
>OMAP-L138 EMIFA Timing - Processors forum - Processors - TI E2E supportforums
> - It seems
> this interval is clock domain change between CPU core and EMIFA.
[Qustion]
Is any document to discribe the interval of clock domain change between CPU core and EMIFA?
