TDA4VM: Boot mcu2_1 only from SBL

Fan,

Unlocking this thread. We will get back to you on this by the end of next week.

Please advise if this issue is still open.

Regards

Karthik

Karthik,

It is still open, please help to look into it. Thanks.

Hi Fan Zhang,

You dont require to use BootApp to load application on mcu2_1. You could just build SBL and convert mcu2_1 in appimage format, and then copy SBL, TIFS and appimage of the application to the SD card. This should be sufficient to boot the application on mcu2_1 using SBL. 

Regards,

Brijesh

Hi, Brijesh,

Yes, I have tried with can_profile_app_tirtos_mcu2_1_release.appimage, it can be booted normally. But, if using can_profile_app_tirtos_mcu2_1_release.rprc to generate app by MulticoreImageGen, it can NOT be booted normally.

Meanwhile, while booting with can_profile_app_tirtos_mcu2_1_release.appimage, I got below log from MCU UART. It seems code for 3 cores were included in can_profile_app_tirtos_mcu2_1_release.appimage. Please help to clarify. Thanks.

SBL Revision: 01.00.10.01 (Oct 18 2021 - 10:02:37)
TIFS  ver: 21.5.0--v2021.05 (Terrific Llam

enter SBL_MulticoreImageParse()

Read Meta Header Start and get the Number of Input RPRC Files

Read all the Core offset addresses
mHdrStr.num_files = 3
i = 0
mHdrStr.num_files = 3
i = 1
mHdrStr.num_files = 3
i = 2

Add Base Offset address for All core Image start offset

Read Meta Header End

Now Parse Individual RPRC files
mHdrStr.num_files = 3
i = 0
srcAddr = 1103625424
mHdrCore[i].image_offset = 48
Copying 0x40 bytes to 0x41010000
Copying 0x4710 bytes to 0x41010100
Copying 0x500 bytes to 0x41017a10
Copying 0x28 bytes to 0x41017f10
Copying 0x10 bytes to 0x41017f38
Copying 0x165f0 bytes to 0x41c9f780
Copying 0xe5e0 bytes to 0x41cb5d70
Copying 0x1700 bytes to 0x41cc9200
Copying 0x1180 bytes to 0x41cca900
srcAddr = 1103625424
entryPoint = 1090584576
mHdrCore[i].core_id = 4
pAppEntry = 1103345560
bootFlag = 1
enter SBL_BootCore()
CoreID = 4
Bootloader cores
Setting entry point for core 4 @0x41010000
Setting entry point for core 4 @0x41010000
mHdrStr.num_files = 3
i = 1
srcAddr = 1103625424
mHdrCore[i].image_offset = 180688
Translating coreid 6 local BTCM addr 0x41010000 to SoC MCU BTCM addr 0x5c10000
Copying 0x1e80 bytes to 0x5c10000
Translating coreid 6 local BTCM addr 0x41011e80 to SoC MCU BTCM addr 0x5c11e80
Copying 0x598 bytes to 0x5c11e80
Translating coreid 6 local BTCM addr 0x41012418 to SoC MCU BTCM addr 0x5c12418
Copying 0x420 bytes to 0x5c12418
Translating coreid 6 local BTCM addr 0x41012838 to SoC MCU BTCM addr 0x5c12838
Copying 0x318 bytes to 0x5c12838
Translating coreid 6 local BTCM addr 0x41012c50 to SoC MCU BTCM addr 0x5c12c50
Copying 0x100 bytes to 0x5c12c50
Copying 0x40 bytes to 0x41c00000
srcAddr = 1103625424
entryPoint = 1103101952
mHdrCore[i].core_id = 6
pAppEntry = 1103345560
bootFlag = 1
enter SBL_BootCore()
CoreID = 6
All other non-bootloader cores
Setting entry point for core 6 @0x41c00000
Setting entry point for core 6 @0x41c00000
CoreID = 6
pAppEntry = 1103345560
mHdrStr.num_files = 3
i = 2
srcAddr = 1103625424
mHdrCore[i].image_offset = 192236
Translating coreid 7 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5d00000
Copying 0x40 bytes to 0x5d00000
Translating coreid 7 local BTCM addr 0x41010000 to SoC MCU BTCM addr 0x5d10000
Copying 0x28 bytes to 0x5d10000
Copying 0xff50 bytes to 0x7001c6f0
Copying 0x8a68 bytes to 0x7002c640
Copying 0x6e78 bytes to 0x700350a8
Copying 0x3388 bytes to 0x7003f800
Copying 0x200 bytes to 0x70046180
Copying 0x200 bytes to 0x70046380
Copying 0x200 bytes to 0x70046580
Copying 0x7d0 bytes to 0x70046980
Copying 0x2000 bytes to 0x700fe000
srcAddr = 1103625424
entryPoint = 0
mHdrCore[i].core_id = 7
pAppEntry = 1103345560
bootFlag = 1
enter SBL_BootCore()
CoreID = 7
All other non-bootloader cores
Setting entry point for core 7 @0x0
Setting entry point for core 7 @0x0
CoreID = 7
pAppEntry = 1103345560
Sciserver Built On: Jun 15 2021 17:03:48
Starting Sciserver..... PASSED
GTC freq: 200000000

hi,

Did you solve the problem ? I meet a same situation like you 

Hi Fan Zhang,

Could you please share the steps to generate rprc file and then appimage? 

I think can profile application does generate appimage that can be copied to SD card to boot it using SBL. Do you see any issue in generating the appimage?

Is above log coming from SBL? SBL will just parse one can profile image for same mcu1_0 core.. Have you included other image in "app" ?

Regards,

Brijesh

Hi, Brijesh,

can_profile_app_tirtos_mcu2_1_release.rprc and can_profile_app_tirtos_mcu2_1_release.appimage were generated at the same time when I build can_profile_app on mcu2_1.

What my customer requested was only load image to mcu2_1 without loading image to mcu2_0. 

The result of my experiments seems it is impossible. And there is description in TRM says "The only restriction is that CPU0 must be in a higher power/reset state than CPU1. For instance, CPU1 cannot be out of reset if CPU0 is not." and "When operating in split mode, CPU0 must be in a higher power/reset state than CPU1." 

So please help to confirm whether my customer's target use case is possible. And please help to descript in more details on how to understand "CPU0 must be in a higher power/reset state than CPU1".

Below are result of my experiments and my speculation. Please help to share your comments. Thanks.

      1. copy can_profile_app_tirtos_mcu2_1_release.appimage(with SBL and TIFS) to SD card, mcu2_1 can be booted normally. But log from MCU UART shows 3 cores are booted, there are mcu1_0(coreid=4), mcu2_0(coreid=6) and mcu2_1(coreid=7). appimage format boots both mcu2_0 and mcu2_1, it is not "load image to mcu2_1 without loading image to mcu2_0"

      2. use sciserver_testapp_tirtos_mcu1_0_release.rprc and can_profile_app_tirtos_mcu2_1_release.rprc to generate multi core image, the command used is "./MulticoreImageGen LE 55 app 4 sciserver_testapp_tirtos_mcu1_0_release.rprc 7 can_profile_app_tirtos_mcu2_1_release.rprc", then copy the generated multi core image(with SBL and TIFS) to SD card, mcu2_1 can not be booted normally