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DRA821U: Whether DRA821 IO retention mode need add 1K ohm pull up resistor at pin T19 (PMIC_WAKE0)?

Tao Han
Expert 5825 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821, TIDEP-01022

Hi Experts:

We are working with customer design DRA821 gateway application based on TIDEP-01022 (https://www.ti.com/tool/TIDEP-01022).

Now we meet problem that IO retention wakeup the T19 (PMIC_WAKE0) keep output low. At TRM and datasheet this pin T19 is not open drain.

Whether we must add pull up 1K resistor to VDD_GPIORET_3V3 power rail at T19 pins for support IOretention feature?

I think configure 0x4301C124 PADCONFIG73 default setting bit28=0b1 bit27=0b0 can pull up T19.

Best Regards!

Han Tao