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DRA829V: Decoupling cap placement

Evan Wang
Expert 4720 points
Part Number: DRA829V

HI All,

I have a question about the placement of the decoupling cap in J721E EVM BRD.

https://www.ti.com/tool/J721EXSOMXEVM 

The EVM BRD (PROC078E8_BRD/PROC078E8A(001)_SCH) use the Via on pad for the capacitors on the bottom layer.

If we are not able to use this way to place those caps, is there any guideline or reference document for it?

Please kindly share your comment with us. 

Thank you.

  • 0
    TI__Mastermind 39570 points

    No - we do not have any reference design without via in pad.  The critical aspect for PCB design of high frequency decoupling capacitors is to minimize the inductance path between the capacitor and the SoC.  This is especially important for high current/low voltage power rails (CORE, CPU, etc).  Typically backside capacitors offer the lowest inductance path due to their distance from the SoC.  Another design technique that can be used is to place decoupling capacitors on the Top/SoC side of the PCB along routing the power plane near the Top/SoC side of the PCB.  While the distance from the ball might be increased, the via lengths can be reduced - minimizing the total inductance.