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Original question:

AM5728: AM5728;TMS320C66x

TMS320C6652: judge CMPY32R1 and DDOTP4H

Links
Intellectual 2205 points
Part Number: TMS320C6652

Hi Team

The image is about TMS320C66x DSP Literature Number: SPRUGH7 November 2010 CPU and Instruction Set

https://www.ti.com/lit/ug/sprugh7/sprugh7.pdf?ts=1638365711612

You can find that Binary is the same, so I hope to determine which instruction it is by inputting binary, so I want to know which registers they belong to and how to judge them?

Best Regards,
William

  • 0
    TI__Mastermind 21915 points

    Dear Customer,

    You are right.  Thanks for the details with the snapshots.

    Let me discuss with the team and get back to you in a day or two.

    Regards

    Shankari G

  • 0 in reply to Shankari G
    TI__Intellectual 2205 points

    Hi Shankari G

    Thanks for your update, I will look forward your reply.

    Best Regards,
    William

  • 0 in reply to Links
    TI__Mastermind 21915 points

    Jiahui Shi-san,

    I have not heard from the team....

    However, using CCS, during run time, we can check the opcode of the two assembly instructions, "CMPY32R1" and "DDOTP4H".

    steps:- During run time, ccs-->view-->Disassembly-->This will display the opcode-->Check the opcodes of both the instructions..

    By any chance, you have already tried this?

    ----

    Would you please, tell us, how you hit this problem....While experimenting with app or just when going through the documentation of CPU instruction set?

    Regards

    Shankari G

  • 0 in reply to Shankari G
    TI__Mastermind 21915 points

    Jiahui Shi-san,

    I received the reply from the internal team, as follows:-

    ---

    The CMPY32R1 and DDOTP4H have different opcode formats (EM2SNC vs. M2SNC) and the opfield is on different bit range ([10:6] vs. [11:7]).
     
    The 32-bit opcode shown in the document for CMPY32R1 is correct:
     
    31
    28
    27
    23
    22
    18
    17
    13
    12
    11
    10
    6
    5
    2
    1
    0
    0001
    dst
    src2
    src1
    x
    0
    01000
    1100
    s
    p
     
     However, the 32-bit opcode for DDOTP4H is incorrect in the document. The correct opcode should be:
     
    31
    28
    27
    23
    22
    18
    17
    13
    12
    11
    7
    6
    2
    1
    0
    0001
    dst
    src2
    src1
    x
    01000
    00000
    s
    p
     
     Regards
    Shankari G