TDA4VM: Can 3 terminals capacitors in TDA4 EVM be deleted for saving pcb area and material cost?

Decoupling provided in the TI EVM l is  he recommendation, as that solution has been tested.  Sufficient power distribution cannot be solved with just specifying quantity and values of capacitors.  It is dependent on many factors - source/supply selection, load requirements, PCB design, capacitor placement, and yes - capacitor selection.

TI typically provides PDN simulation requirements - which are a better mechanism for validating the power distribution.  It specifies the maximum IR drop between the power source and load.  It specifies the maximum loop inductance, which is the connection between the load and the decoupling capacitors.  Its specifies the target impedance, which is the overall path's behavior across frequency.  Together, these requirements ensure the noise levels during transients will be maintained.

After meeting these PDN simulation requirements - it may be possible to reduce the amount of decoupling. We have studies that show this.   However - it is strongly recommended that the decoupling not be reduced until simulations shown the PDN meets all the requirements.

Thanks.

Can TI offer the simulation document and project files?

Thanks.

We want to simulate PDN, so we want to know if TI can offer PDN simulation documents and project files.

Below are the simulation targets for TDA4VM PCB designs.  We don't have any project files - I need to check if we have any other documentation.

Thanks a lot!

I found a document in CDDS, in which the tool Ansys SiWave was used, so I think TI has the SiWave project file, similar to the BRD file of PCB, but can TI provide it? Thanks.

No - we don't have any SiWave project files to provide to customers.