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TDA4vM EVM Power Supply

H-J
Intellectual 300 points

Hello，

In the TDA4 EVM, a lot of three-terminal capacitors are used in the TDA4 power supply.

Can we use ordinary ceramic capacitors instead in our design?

These three terminal capacitors are too difficult to purchase.

Thanks！

  • 0
    TI__Mastermind 19190 points

    The three terminal capacitors can be replaced by ordinary ceramic capacitors.

    We have found that we can use fewer three terminal capacitors than ordinary ceramic capacitors so be sure to note that you cannot simply replace them one-for-one.

    Kevin Lavery

  • 0 in reply to Kevin Lavery
    Intellectual 300 points

    Thanks for your reply.

    Is there a recommended replacement ratio for three terminal capacitors using ordinary ceramic capacitors?

  • 0 in reply to H-J
    TI__Expert 6195 points

    As mentioned, you can use standard 2-terminal MLCC caps instead of the newer, very-low ESL 3-term caps. I would expect you’ll need ~6-8x more 2-term caps to achieve similar PI performance. 

    I’ve attached a PDN Dcap optimization study that compares 2-term vs 3-term Dcaps conducted by Murata using our J6Plus Reference Design PCB. In summary, using very-low ESL 3-term caps on SoC & DDR power rails allowed the total qty of Dcaps to be reduce by 38pcs (22 less for SoC & 16 less for DDR), leading to 37% Dcap area reduction while achieving similar ZvF responses per rail & providing a similar BOM cost. The reduction in total Dcap qty helps to improve power rail routing while reducing "Swiss-chesse" impact of vias on power routes.

    To avoid single source issues, we have identified 2 capacitor manufacturers (Murata & TDK) with same size (0603) 3-term, automotive qualified caps PNs (NFM18HC106D0G3 & YFF18AC0G475M). We’ve conducted PI simulations to verify that either cap provides desired ZvsF response for J7ES PI even though these caps have different capacitance values (10uF & 4.7uF).

    Ultimately, the PCB design & Dcap scheme combine to form your system's Power Distribution Network (PDN) that should meet recommended SoC PI targets for robust processor operations. Each PCB design has a "unique finger-print" based upon power routing & layer assignments, via qtys & locations, Dcap mounting/loop inductance, etc. As a result, an optimized Dcap scheme can vary from one PCB design to another but should provide a system PDN that meets PI performance targets when combined together.

    2273.6153.Murata Capacitor for Jacinto 7.pdf