• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 101 subscribers
  • Views 109 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM-Q1: the connection and placement of 3-terminal capacitor used in the EVM

Xingyu Zhu
Expert 3625 points
Part Number: TDA4VM-Q1

Hi expert,

Could you please help to share your comments about below 2 questions? Thanks.

1. There are 2 connection way of 3-terminal capacitor. Customer feedback the cap vendor recommend use series connection, but EVM uses parallel connection. Could you please tell me the difference and our consideration?

2. Based on my understanding, the 3-terminal cap should be placed on the bottom layer to minimize the power trace length to get the best PDN performance. But some of them are placed on the top layer, could you please explain? Thanks. 

Best Regards,

Xingyu Zhu

  • 0
    TI__Mastermind 47440 points

    Q1:  The different configuration of the 3-terminal capacitor serve different purposes.  Our designs use the 3-terminal capacitor for very low inductance decoupling, thus use the parallel configuration.

    Q2:  The lowest inductance path between capacitor and power pins may be different for different designs.  If placing capacitors on backside of the PCB, goal is to minimize the any trace connecting to the via - thus leaving only the via inductance.  Sometimes placing capacitors on the top side of the PCB (same side as processor) can shorten the via, and reduce the inductance path (assuming a plane segment near the top layer is used to access the power pins).  Both mechanism can be effective if properly implemented.

  • 0 in reply to Robert Eschler
    TI__Expert 3625 points

    Hi Robert

    Thanks for your reply. About Q2, our customer has some further questions.

    Robert Eschler said:
    Sometimes placing capacitors on the top side of the PCB (same side as processor) can shorten the via, and reduce the inductance path (assuming a plane segment near the top layer is used to access the power pins)

    They think even though placing on the top side can shorten the Via, compared with the increased trace length, this affection may not be very obvious. So the advantage of 3-terminal capacitor cannot be made the most of, 2-termianl can also be used here. Is there other special consideration of using 3-terminal cap on the top side? 

    Could you please respond to their question? Thanks.

  • 0 in reply to Xingyu Zhu
    TI__Mastermind 47440 points

    3 terminal capacitors have lower package inductance comparted with 2 terminal capacitors.  When package inductance is combined with the inductance of the PCB trace (for total loop inductance)..3term will likely be lower than a 2term capacitor with same inductance of PCB trace.  The 3term vs 2term comparison is separate from the top vs bottom decoupling location.