void PLL_Configuration()
{
int i; //JFV 30/11/2006 here for the wait loops
//PLLCSR &= 0xFFFFFFFE; // set PLLEN to 0
PLLCSR = 0x40; // set PLLEN to 0
for (i=0; i<5; i++)
{} // wait for 4 CLKIN cycles
//PLLCSR |= 0x00000008; // set PLLRST to 1
PLLCSR = 0x48; // set PLLRST to 1
//Registre PLLDIV0, division par 9 => PLLREF
PLLDIV0 = 0x0008008; // 60MHz/9=6.66Mhz
//Registre PLLM, multiplication par 18 => PLLOUT
PLLM = 0x00000012; // 6.66MHz*18=120MHz
//Registre OSCDIV1, division par 1 => CLKOUT3
OSCDIV1 = 0x00008002; //Division par 3 (60Mhz/3 = 20 Mhz)
//Registre PLLDIV1, division par 1 => SYSCLK1
PLLDIV1 = 0x00008000; // 120Mhz/1=120MHz
for (i=0; i<9; i++)
{} // wait for 8 CLKIN cycles
//Registre PLLDIV2, division par 2 => SYSCLK2
PLLDIV2 = 0x00008001; // 120Mhz/2=60MHz
for (i=0; i<9; i++)
{} // wait for 8 CLKIN cycles
//Registre PLLDIV3, division par 2 => SYSCLK3
PLLDIV3 = 0x00008001; // 120Mhz/2=60MHz
for (i=0; i<9; i++)
{} // wait for PLL to reset (125ns)
//PLLCSR &= 0xFFF7; // set PLLRST to 0
PLLCSR = 0x40; // set PLLRST to 0
for (i=0; i<11280; i++)
{} // wait for PLL to lock 188us max
//PLLCSR |= 0x00000001; // set PLLEN to 1
PLLCSR = 0x01; // set PLLEN to 1
}
