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AM3354: About EMIF tool for single use of DDR3, and tDQSS Margin Adjustment

user1201164
Expert 1770 points
Part Number: AM3354

Hi,
We are getting some questions from our customers.
They are using AM3354 with a single DDR3.
At first, they asked if there is a way to adjust the CLK and DQS skew, as they are large and the margin is not small.
In response, I asked them to check if they were designing according to the dataSheet guidelines, and to change the register values using the EMIF tool.
However, when the value calculated by the tool was set, tDQSS=833ps and access became impossible within a few seconds.
After Software Leveling, tDQSS was set to 600ps and the system started to work, but he was concerned about the small margin.

The questions I'm getting from them are
1) I read in the EMIF tool that they don't need Software Leveling for single use of DDR3, is this correct?
2) In the current spreadsheet, Invert Clkout seems to be a fixed value (=1), is this correct? In past spreadsheets, it was 0 or 1 depending on the relationship between CK and DQS wire lengths.

Also, the margin of tDQSS is currently low. What register do I need to change to adjust this value?

  • 0
    Expert 1770 points

    Hi,

    I would like to know how things are going about the issue.

    Best Regards,

    Kouji Nishigata

  • 0
    TI__Guru* 80260 points

    Yes, they shouldn't need software leveling if using a single DDR3 and address/data are point to point.  The fixed value for invert clkout is correct.  This was updated from older spreadsheet as it provided more margin.

    Have them ensure that the CLK and DQS trace lengths represented in the spreadsheet are correct.  These are critical to obtain the correct delay values.  Ensure to include the full trace length including via lengths.  

    Is the violation occurring on both DQS0 and DQS1?  Is the measurement during a write or a read?  Where on the trace are they probing the signal?

    Regards,

    James

  • 0 in reply to JJD
    Expert 1770 points

    Hi, James

    Thanks for the answer.

    The customer contacted me and said that he adjusted the parameters and it works now.
    However, he wants to know the registers for each amplitude for verification.
    As far as I can see, the following registers are involved, but please let me know if there are any other registers that are involved or not.
    - 10h SDRAM_REF_CTRL
    - 14h SDRAM_REF_CTRL_SHDW
    - 18h SDRAM_TIM_1
    - 1Ch SDRAM_TIM_1_SHDW
    - 20h SDRAM_TIM_2
    - 24h SDRAM_TIM_2_SHDW
    - 28h SDRAM_TIM_3
    - 2Ch SDRAM_TIM_3_SHDW

    Best Regards,

    Kouji Nishigata

  • 0 in reply to user1201164
    Expert 1770 points

    Hi,

    I would like to know how things are going about the issue.

    Best Regards,

    Kouji Nishigata

  • 0 in reply to user1201164
    TI__Guru* 80260 points

    Sorry, i don't understand the question: "he wants to know the register for each amplitude for verification"?  If he wants to know which registers changed to fix the issue, he should do a before/after comparison in with each of the registers in the EMIF tool.  

    Regards,

    james