AM3352: DDR3 compliance test failed at tDQSS

Kz777

Part Number: AM3352

Hi Champs,

We failed tDQSS compliance failed for DDR3 compliance test.

Usually, tDQSS measure delay between CLK and DQS during writing.

This measurement value is 0.26CK marginal fail against limit +-0.25CK@800Mbps , +-0.27CK@1600Mbps

I think this issue can be fix by SW leveling.

Could you please tell us what kind of leveling parameter adjust for this fail ?

See this picture

0 Brad Griffis over 6 years ago

That timing will be impacted by these structures in u-boot:

static const struct ddr_data ddr3_BOARDNAME_ddr_data = {
	.datardsratio0 =	0x00000040	,
	.datawdsratio0 =	0x00000081	,
	.datafwsratio0 =	0x000000E4	,
	.datawrsratio0 =	0x000000C1	,
};

static const struct cmd_control ddr3_BOARDNAME_cmd_ctrl_data = {
	.cmd0csratio =	0x00000100	,
	.cmd0iclkout =	0x00000001	,
	.cmd1csratio =	0x00000100	,
	.cmd1iclkout =	0x00000001	,
	.cmd2csratio =	0x00000100	,
	.cmd2iclkout =	0x00000001	,
};

What are the lengths of CLK, DQS0 and DQS1? I assume you're using a single 16-bit DDR, right?

0 Kz777 over 6 years ago in reply to Brad Griffis

Hi Brad,

Thanks for mail.

I send CLK setting detail to your private mail. Could you please check it ?

0 Brad Griffis over 6 years ago in reply to Kz777

I've sent back some updated values. Please try them out and provide an update.

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