I'm working with a customer that is building a SOM module with the DRA821U and they want to use buffers (w/enable) and/or muxes to make sure the BOOTMODE pull-ups are correct before connecting up the I/O lines to the rest of their board. This is similar in fact to what we have done in some of our reference designs.
When I look at the power on sequence diagram in the datasheet, there is a note that the BOOTMODE is latched on the rising edge of the PORz line(s), and that the setup and hold times "shown" must be be respected. All I can find for these setup and hold timings are an imprecise diagram. I don't see actual setup and hold times listed anywhere. If I look at the reverence designs, it looks like we control our buffer enables off of the PORz reset line(s), which I would think violate at least the hold timing according to the sequence diagram, which shows at least a 7 LPOSC0 clocks of hold time. I don't see how our reference designs could be meeting the requirements as the diagram shows, though the diagram is very imprecise.
What are the actual requirements here?
Thanks,
Stuart
