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66AK2H14: DDR3 ibis models

Bruno B
Expert 1230 points
Part Number: 66AK2H14

Hi,

When using the "66ak2h14_r1p4.ibs"  file for DDR3A interface simulations we found several driver models that can be used

- PDDRIO_D3FP3_34

- PDDRIO_D3FP3_40

- PDDRIO_D3FP3_48

- PDDRIO_D3FP3L_34

- PDDRIO_D3FP3L_40

- PDDRIO_D3FP3L_48

I have 3 questions :

1) can you tell which models should be used when the external devices are DDR3L chips supporting 1V5 supply such as Micron MT41K256M16TW-107 therefore used as DDR3 device ?

2) which value should take the IODDRM bit in the PGCR1 DDR3 memory controler when external device is a DDR3L chip supplied with 1V5 such as explained in 1)

3) is there a relation between the ibis model category to be used ("D3FP3" or "D3FP3L") and the IODDRM value that must be set when configuring the controler?

with best regards,

Bruno

  • 0
    TI__Guru 51892 points

    You should use the PDDRIO_D3FP3_34 for address, control, command and clock routing groups, and PDDRIO_D3FP3_40 for the data bus.

    The 3L models are for 1.35V operation and should not be used.

    Refer to these two app notes for details:

    Keystone II DDR3 Initialization

    DDR3 Design Requirements for KeyStone Devices (Rev. C)

    Regards,

    Kyle

  • 0
    TI__Mastermind 25535 points

    Bruno,

    Q: 1) can you tell which models should be used when the external devices are DDR3L chips supporting 1V5 supply such as Micron MT41K256M16TW-107 therefore used as DDR3 device ?

    Ans: It is better to enquire/post a question to "Micron". Because, though the DDR3L ( 1.35 V ) chips supports 1.5V and hence you are planning to configure it as DDR3 device. 

    ------------

    Q 2) which value should take the IODDRM bit in the PGCR1 DDR3 memory controler when external device is a DDR3L chip supplied with 1V5 such as explained in 1)

    Ans:  According to DDR3 or DDR3L, 

    In register, DDR3_PGCR1, value of IODDRM (bit 7:8) should be set as 1 for "DDR3"

    and the value of IODDRM (bit 7:8) should be set as 2 for "DDR3L". 

    As per the data sheet : https://www.ti.com/lit/ug/spruhn7c/spruhn7c.pdf

    -------------------------------------

    Q 3) is there a relation between the ibis model category to be used ("D3FP3" or "D3FP3L") and the IODDRM value that must be set when configuring the controller?

    Ans : Yes, while configuring the controller, the "IODDRM " value should be set.

    It is better to stick to one configuration ( either DDR3L or DDR3 ) both in hardware and software configuration.

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Expert 1230 points

    Hi M.Shankari,

    Q1) My question was about 66AK2H14 output drivers ,  that is drivers representing ADDRESS, and COMMAND bus behaviour. This should be specific to the TI part. THere is no reason Micron would give recommandations about this I think.

    Q2/Q3) according to Kyle answer, it becomes clear that DDR3L models being forbidden we must use DDR3 models and therefore set IODDRM to DDR3. Agree ?

    with best regards,

    Bruno

  • 0 in reply to Bruno B
    TI__Guru 51892 points

    Bruno,

    Q2/Q3:  Agree.  The SoC only supports 1.5V operation.  In general most DDR3L components are backwards compatible with 1.5V operation.  You should confirm that for the memory you choose.

    Regards,
    Kyle

  • 0 in reply to kcastille
    TI__Mastermind 25535 points

    Kyle,

    But, in the SoC datasheet, page no: 278 (https://www.ti.com/lit/ds/symlink/66ak2h14.pdf) , it says, 

    -----

    11.9.1 DDR3 Memory Controller Device-Specific Information

    The 66AK2Hxx includes one 64-bit wide, 1.35-V / 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS. " 

    ----

    Which means, it should support both ( DDR3 and DDR3L ) right?

    Regards

    Shankari G

  • 0 in reply to Shankari G
    TI__Mastermind 25535 points

    Bruno,

    We enquired the internal team and got reply as below.

    The 66AK2Hxx  SoC supports both DDR3 and DDR3L as per the Device-Datasheet. (page no:278, www.ti.com/.../66ak2h14.pdf)

    But the same information is not updated  here, DDR3 Design Requirements for KeyStone Devices (Rev. C) ( https://www.ti.com/lit/an/sprabi1c/sprabi1c.pdf )

    If DDR3L is used, 3L models can be used.

    Please revert if there are any further questions.

    Regards

    Shankari G

  • 0 in reply to Bruno B
    TI__Mastermind 25535 points

    Bruno,

    These are the two things, which I recommended, to enquire Micron.

    1. When DDR3L is used as DDR3 ( with 1.5 V), the same timing parameters are applicable for DDR3 as well ?

    Because the timing parameters given in the "Micron-datasheet" specifies only for DDR3L.

    Micron datasheet - 4Gb: x4, x8, x16 DDR3L SDRAM (micron.com)

    2.  As per the part number, "MT41K256M16TW-107 XIT ", 107 implies, the speed grade as DDR3-1866 with "tCK– 1.07ns @ CL = 13".

    If your operating speed grade is 1600 MTS, which "speed-bin table" is to be used for register calculation?? 

    Either "Table 55: DDR3L-1600 Speed Bins" ?? or "Table 56: DDR3L-1866 Speed Bins" ?? 

    Because, it says it is backward compatible for "The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E). "

    I hope, I clarified, why we need to enquire micron....

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Expert 1230 points

    Hi

    1. When the DDR3L component is used with 1V5 power supply, the applicable timing parameters are those of the DDR3 datasheet

    2. The speed bin table to use is the  DDR3/1600

    regards,

    Bruno