AM5728: PCIE Deassert INT function of sitara(Again)

Hi,

Sorry for rush you. Is there any update? Our customer needs answers to move on to the actual design, so it would be helpful if you could tell us the status.

Please let us know if there is any information missing or unclear.

Best regards,
O.H

Hi,

Sorry for rush you. Is there any update? Our customer needs answers to move on to the actual design, so it would be helpful if you could tell us the status.

Please let us know if there is any information missing or unclear.

Best regards,
O.H

O.H., 

sorry for the delayed response. 

on your questions - we do not support DMA scatter and gather on the PCIe interface. Addressing has to be continuous when DMA over the PCIe link. 

On deassert INTA, I assume you want the PC to signal the completion of writing data to FPGA what is attached to the GPMC interface of the AM57. I am aware on AM65 we have TI-specific implementation that allows RC to send a interrupt to the EP, but just checked in AM57, INTD is only possible for EP->RC. I will check with the team to confirm on AM57. 

regards

Jian

Hi Jian,

Thank you for your support. I understood about scatter and gather. We look forward to receiving additional information.

Best regards,
O.H

Hi Jian,

We have received feedback from a customer. The customer had previously used TI's Sitara AM572x series in EndPoint mode with a PCI Express connection. The specification was that the INTA that were asserted from the SoC to the host side could not be cleared (deasserted) from the host side, so the interrupts kept coming in to the host side. The AM572x series PCI Express is designed with the assumption of RootComplex, which is why it has the above specification.

Has the above specification been improved in AM65?

Best regards,
O.H

Hi Jian,

The customer was checking AM65 and asked an additional question. Could you please tell us about the following question?

Q:Is it possible to do the following with the AM65x series?
In EndPoint mode, map the "PCIE0_DAT" area including the "PCIE_EP_LEGACY_IRQ_CLR" register to the BAR area. This will allow deassert of INTA directly from the upper PC.

jian35385 said:

On deassert INTA, I assume you want the PC to signal the completion of writing data to FPGA what is attached to the GPMC interface of the AM57. I am aware on AM65 we have TI-specific implementation that allows RC to send a interrupt to the EP, but just checked in AM57, INTD is only possible for EP->RC. I will check with the team to confirm on AM57. 

The following is a supplement.

The AM57 series had the "PCIECTRL_TI_CONF_INTX_DEASSERT" register for deasserting INTA in a distant location on the memory map from the normal PCIe Configration register. Therefore, it could not be mapped to the BARx area from a high-level perspective, and INTA could not be deasserted directly from a high-level perspective.
The customer's product generates an interrupt to the SoC by accessing a register in the FPGA located in the GPMC that is mapped to the BARx area from a high-level perspective. The SoC then deasserts INTA in the interrupt process, solving the problem as a stopgap measure.
The performance was fatally poor as an implementation of an add-on card (PCI Express EndPoint) to a PC, and problems continued to appear with regard to the handling of interrupts at the upper level. (Interrupts would keep coming in until INTA was deasserted on the high-level side. Therefore, the SoC must wait within the upper-level interrupt process until the SoC deasserts INTA.)

Best regards,
O.H

Hi,

Sorry for rush you. Is there any update? Our customer needs answers to move on to the actual design, so it would be helpful if you could tell us the status.

Please let us know if there is any information missing or unclear.

Best regards,
O.H