Other Parts Discussed in Thread: AM2434
edit: typos
Dear sirs,
we're a company that manufactures high end COBOTs, both the mechanical and the electric/electronic parts.
In the following, I describe the project we're involved in, and furthermore the reasons for our help request.
The project status
Currently, we have developed a POC servo board that implements these features:
- a so-called working CPU that implements
- MANDATORY: FOC motor control
- MANDATORY: current, speed and position control
- MANDATORY: EtherCAT slave interface
- right now, we use a dedicated chip to implement the EtherCAT slave interface
We are now implementing a first production release of the servo board, where these features are added:
- MANDATORY: two functional safety cores must be added
- one of them must be a checker CPU, and must NOT be in the same chip as the working CPU
- they must handle FSoE and redundant safety digital inputs
- IEC 61508 must be handled
- 2x BISS encoder interface
- if possible, one for each of the safety cores
- more horsepower to the working CPU to implement real time features, the likes of collision detection, model following etc
- due to physical constraints, the board itself isn't very big, so the BOM should be as simple as possible
- whenever possible, other industrial communication buses (TSN, ProfiNET, ...) should be implemented
We have an offer for an architecture where seven main chips are involved:
- the working CPU
- two safety CPUs
- the EtherCAT slave interface chip
- a CPU that splits/merges the working data (to/from the working CPU) and the safety data (to/from the safety CPUs)
- a couple of BISS interface chips
The CCU
Furthermore, we are looking to implement a control unit (CCU), de facto a board that implements these features:
- the CCU sits between an industrial PC and the EtherCAT cascade of the servo drive boards
- the CCU implements a real time EtherCAT master
- the PC feds the trajectory data stream through a CCU Ethernet port
- the CCU implements ROS or micro-ros
The TI solution
After the "seven-chips proposal", that right now is the only one we have, we checked if we might reasonably reduce the BOM complexity.
We looked into the AM65x and the AM64x Sitara families, where these important features are available:
- isolated real time cores for functional safety handling
- EtherCAT and BISS interface through the PRUs
- EtherCAT master available from Acontis, with what seems a very low jitter of +/- 40 ns
- FOC motor control library available
- IEC 61508 features kept in mind in the architecture
- it seems that the Sitara family is born as a servo drive CPU, as stated in your spry330c.pdf leaflet:
- Utilizing SitaraTM Processors and Microcontrollers for Industry 4.0 Servo Drives
We wanted to explore if TI could be a solution for both the servo drive and the CCU board.
The questions
We are looking for help about these questions:
- with respect to the AM64x or AM65x
- do they represent, in your opinion, the best / a good TI solution for our servo and CCU projects?
- is it true that they can implement in the same core the following features:
- single axis FOC motor control
- EtherCAT slave
- BISS encoder interface
- just 1 or even 2?
- an isolated core for the functional safety handling
- it handles the FSoE stack
- it reads these input values
- BISS encoder(s)
- current values
- safe digital input values
- it sets this output
- STO digital output
- it requests the working core for a deceleration ramp
- an isolated core for current control loop?
- are they readily available in production, right now and / or in the near future?
- or, if the AM6x series is not a good solution:
- are in the TI bouquet other processors / solutions you can suggest us?
- please keep in mind that the EherCAT interface is mandatory, so a solution using for example the TI FSI bus cannot be used
- are in the TI bouquet other processors / solutions you can suggest us?
BR
Michele Sponchiado