AM6442: OSPI Clock

Brian, would like you to clarify the boot mode you are using.  NO BOOT mode is a mode in which the ROM does not execute any booting.  I think what you mean is that you are in xSPI boot mode with SFDP enabled.  During data transfer, this mode will operate at 50MHz, but initially the ROM will operate much slower (6.25Mhz) in order to properly read the SFDP and initialize the interface.  Can you read CTRLMMR_MAIN_DEVSTAT (address 0x43000030) and post here?  This will determine what the AM64x read as a bootmode.

Regards,

James

Hello James,

I measured the OSPI clock during start up.

We enabled the SDFP in xSPI bootmode, that means the ROM starts the operation in 1S-1S-1S mode and reads the SDFP header from the flash.

In 1S-1S-1S Mode the switching frequency of the clock should be 50MHz, but the measurement shows 41,67MHz. (see scope1)

 Scope1:

After the SFDP read from the ROM, they switch to 8D-8D-8D Mode. They frequency I measured is 20,83MHz instead of 25MHz. (see scope2)

Scope2:

I also saw a very strange behavior. After the SFDP read the clock alternates between 20,83MHz (scope2) and 166MHz (scope3).

Scope3:

Is this the right behavior? Please correct me if I am wrong.

My understanding that the xSPI boot configuration fields as TRM however on our real HW, the xSPI clock doesn't look like the TI's spec. I don't know why?

May be my custom hw layout is not good, or other reasons.....

Did you measure the xSPI clock in the xSPI boot mode on EVM? Can you recommend me something about that?

Many thank you for your response and your investigations.

Brian,

Brian, please see the previous post, asking for the value of the CTRLMMR_MAIN_DEVSTAT register.  Also, check you system input clock.  What is the frequency?

Regards,

James

Hello James,

I logout the CTRLMMR_MAIN_DEVSTAT

CTRLMMR_MAIN_DEVSTAT (4300 0030h)

spl_boot_device: devstat = 0xEFF3

=> b1110111111110011

PLL = 25MHz
xSPI boot mode
and Backup boot mode is UART

How can I check the system clock?

Thanks,

Brian.

THis should be probed on the board.  It is the main crystal input clock connected to MCU_OSC0

Regards,

James

Hello James,

This is waveform of crystal input clock on MCU_OSC0

Thanks,

Brian

I'm not sure why you are observing those frequencies.  Can you ensure that you probe the clock immediately following a power sequence?  Also, you boot mode pins are set for 8D-8D-8D mode initially (BOOTMODE7).  Can you switch to 1S-1S-1S mode and observe the clock?  Which xSPI device are you using?

Regards,

James

Hello James,

Our hw team want to check our custom board about the booting up. This effects on the booting time of system. I am sure measuring is exactly as you see scope1, 2 and 3.

xSPI device is S28HS01GT.

I'm looking for a scope shot of the clocks immediately after a powerup.  I don't know how far into the boot is scope 1,2,3.  Certainly scope3 is beyond the ROM and into u-boot since you see 166MHz.  It is possible that the others are as well.

Regards,

James