DM648 REFCLK jitter

David Meixner

Other Parts Discussed in Thread: TMS320DM647

Can you clarify the jitter specification for the REFCLK input? Table 6-82 of the DM648 datasheet says 50 ps pk-pk for a 1.25 Gbps line rate. How does this translate to the input clock if a multiplication factor of 20 is used? 50/20= 2.5 ps?

over 14 years ago

0 David Meixner over 14 years ago

TI__Expert 4010 points

David Meixner said:

Can you clarify the jitter specification for the REFCLK input? Table 6-82 of the DM648 datasheet says 50 ps pk-pk for a 1.25 Gbps line rate. How does this translate to the input clock if a multiplication factor of 20 is used? 50/20= 2.5 ps?

Has anyone had a chance to look at this? Thanks.

0 srirami over 14 years ago in reply to David Meixner

TI__Expert 8260 points

Following are the comments from H/W engineer:

I assumed that the 50 ps pk-pk applied regardless of which multiplier is used. The table doesn’t say anything about depending on the multiplier.

Regards, Srirami.

0 Daisuke Maeda over 12 years ago in reply to srirami

Guru 20155 points

Hi,

For REFCLKP/N clock rate the possible suggested is either 50MHz or 62.5MHz or 125MHz, and the corresponding Line Rate is 625Mbps or 1250Mbps.

TMS320DM647/DM648 DSP 3 Port Switch Ethernet Subsystem User's Guide (Rev. B)
http://www.ti.com/lit/ug/spruf57b/spruf57b.pdf
1.4 Clocks (Page 19)

Does the 50 ps pk-pk apply regardless of which clock rate is used?

Does the 50 ps pk-pk apply when Line Rate is 625Mbps?

Best regards,

Daisuke

0 Daisuke Maeda over 12 years ago in reply to Daisuke Maeda

Guru 20155 points

Hi,

I new posted.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/t/265573.aspx

Best regards,

Daisuke

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DM648 REFCLK jitter