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AM6442: IEP SYNC adjust phase

Steven Hansen
Intellectual 621 points
Part Number: AM6442

Hello, I'm attempting to use the SYNC feature of the PRU-ICSSG IEP peripheral to generate a periodic output pulse that is synchronized with an external FPGA. The FPGA communicates with the PRU using SPI, and some of the SPI data will tell the AM6442 how much to adjust the phase of the SYNC output to maintain synchronization.

So far I've managed generate an output on SYNC0 at the desired frequency using cyclic mode. However, I cannot figure out how to adjust the phase of the SYNC output. Adjusting CMP1 doesn't work, and the TRM has a comment on page 3586 that says "Cyclic generation cannot be used for network time synchronized applications because only the CMP1/CMP2 hit occurs in the compensated time domain." But the TRM doesn't provide any alternatives.

What ways are there to adjust the IEP SYNC phase? I believe this must be possible because the TI PRU Ethernet firmware on the AM6442 supports IEEE 1588 with a 1pps output. What I'm trying to do is very similar. How does the TI firmware adjust the phase of the SYNC signal?

  • 0
    TI__Guru**** 155689 points

    Hello Steven Hansen 

    Thank you for the query. 

    Let me check internally and update you.

    Please expect a delay in response due to the upcoming US holiday.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 155689 points

    Hello Steven Hansen 

    I see that You mentioned the below in the query. Could you please provide some additional details on how you have implemented the below function. 

    So far I've managed generate an output on SYNC0 at the desired frequency using cyclic mode. 

    Thank you for the inputs that could help us analyze.

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    Intellectual 621 points

    Hi Sreenivasa,

    I was able to solve this issue on my own by doing the following:

    1. Putting the IEP SYNC in single-shot mode

    2. Updating the CMP1 registers manually (ie moving them forward to the next sync event) after each sync event occurs. To do this, I check the timer every so-often to see if it has reached the trigger point. I defined the trigger point as 1/2 a period after a sync occurs so the SYNC pin has transitioned high and then low again since I'm generating a symmetrical SYNC waveform.

    3. To apply the new CMP1 value, I found that it was necessary to clear and then set the SYNC_EN, SYNC0_EN, and SYNC1_EN bits via the IEP_SYNC_CTRL_REG register.

    4. Use the IEP compensation feature via IEP_COMPEN_REG or IEP_SLOW_COMPEN_REG to periodically change the IEP clock rate rather than adjust the SYNC trigger points to achieve synchronization.

    Point 3 was the most difficult to figure out as the TRM is light on details in this section. It would be great if TI could update the TRM to include more information on single-shot and cyclic modes, and specifically that new compare values don't take affect in single-shot mode unless the SYNC_EN and SYNCx_EN bits are cleared and then set again. This makes sense in hindsight, but wasn't immediately obvious when trying to figure out how to make this work.

  • 0 in reply to Steven Hansen
    TI__Guru**** 155689 points

    Hello Steven Hansen 

    Firstly, thank you very much for the efforts you have put in resolving the issue.

    I also want to thank you for the detailed explanation.

    Noted on the inputs in updating the TRM.

    You have a great day.

    Regards,

    Sreenivasa