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Hi.
My customer is testing the TDA4 CAN on their PCB.
They already verified the CAN bus on the DRA821U of their pcb. It works well.
But, they migrate the code from DRA821U to TDA4. they found the CAN TX has no signal, meanwhile, CAN loop has no signal.
Any comments? (They are testing SDK8.2)
THanks.
BR Rio
Porting TDA4 in our PCB and test MCU_MCAN0 in MCU1_0 with IPC sample code.
1. Remove MCAN related item in LINUX device tree (DTS).
2. Add EN & STB PIN setting in RTOS pinmux setting.
3. Refer sample code : pdk/packages/ti/csl/example/mcan/mcanEvmLoopback/mcan_evm_loopback_app_main_k3.c to test CAN message.
static int32_t App_mcanRegisterIsr(uint32_t mcanInstAddr)
{
int32_t configStatus = STW_SOK;
/* Running Code from Mcu R5 */
/* MCU MCAN Inst 0 */
configStatus = App_mcanRegisterInterrupt(MCU_MCAN0_TX_INT_NUM, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(MCU_MCAN0_RX_INT_NUM, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(MCU_MCAN0_TS_INT_NUM, &App_mcanTSIntrISR);
if(STW_SOK != configStatus)
{
UART_printf("CrossBar/Interrupt Configuration failed.\n");
}
else
{
UART_printf("CrossBar/Interrupt Configuration done.\n");
}
return configStatus;
}
We met the problem:
1. call APP_mcanLpbkTest() CAN loopback test Fail, because TX/RX ISR does not trigger. (for other normal test, CAN TX/RX ISR also does not trigger.)
it will stop on the while loop.
while (gMcanIsrIntr1Flag)
{}
gMcanIsrIntr1Flag = 1U;
Why TX/RX ISR does not trigger, could you provide some suggestion?
Thanks.
Hi Jay,
Are you getting an error while registering the interrupt? Or is this successfully getting registered but somehow not getting triggered?
Is this issue only seen for MCU MCAN0 or for MCU MCAN1 as well?
Regards
Karan
Hi Karan,
1.this is successfully getting registered but somehow not getting triggered.
2.MCU MCAN0 and MCU MCAN1 all have this problem.
Thanks.
Hi Rio, Jay,
1. When you have moved from DRA821 to TDA4VM, did you take care of the interrupt numbers?
2. Can you check the MCAN IPs raw interrupt status? Check the register MCAN_IR?
There could be an issue where the MCAN IP's interrupt is not correctly hooked to the R5F interrupt but even in that case the MCAN_IR should give the correct status.
3. Have you been able to run this example on the TDA4VM EVM? The loopback test, at least from the CAN perspective, should not be board dependent as the transceiver doesn't come in the picture during an internal loopback test.
Regards
Karan
Hi Karan,
1. DRA821 and TDA4VM are the same and use the below interrupt number:
#define MCU_MCAN0_TX_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define MCU_MCAN0_RX_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define MCU_MCAN0_TS_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define MCU_MCAN1_TX_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_MCAN_LVL_INT_0)
#define MCU_MCAN1_RX_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_MCAN_LVL_INT_1)
#define MCU_MCAN1_TS_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
2. what is "MCAN IPs raw interrupt status", could you explain more detail or give some example?
3. I had tested CAN PASS with /pdk_08_01_00_36/packages/ti/board/diag/mcan/ on TDA4VM EVM before, but not test CAN with pdk_08_02 on TDA4VM EVM.
Thanks.
Hi,
2. what is "MCAN IPs raw interrupt status", could you explain more detail or give some example?
This is the MCAN_IR register.
The way a core gets an interrupt is as below:
1. IP generated an interrupt - raw interrupt
2. IP's raw interrupt is then masked with the enable bits, if the interrupt is enabled then it will drive the interrupt line to the core.
3. The Core gets an interrupt on the dedicated line from the IP (or via an interrupt router). If this interrupt is registered with an ISR on the Core, then the the ISR fires.
I would think the issue is with 3 and that is why MCAN_IR register should still show a valid status.
Regards
Karan
Hi Karan,
I read the MCU_MCAN0_CFG IR&IE&ILS&ILE address value, like above. Check with Doc, it seems to be OK.
But Why ISR does not been triggered? (you have our source code in mail attached file, please help to check the code, and provide the right solution)
Thanks very much.
Regards
Jay
Notes:
Regards
Karan
Hi Karan,
We can reproduce this issue on TDA4VM EVM with SDK 8.0.1 & 8.0.2.
|
|
Polling TX |
Polling Rx |
Interrupt TX |
Interrupt RX |
loopback |
|
Test Case1: board_diag_mcan @pdk_jacinto_08_01_00_36 |
OK |
FAIL |
FAIL*(1) |
FAIL*(2) |
NA |
|
Test Case 2: csl_mcan_evm_loopback_app @ pdk_jacinto_08_02_00_21 |
FAIL*(3) |
FAIL*(3) |
FAIL*(3) |
FAIL*(3) |
FAIL*(3) |
|
Test Case3: board_diag_mcan + pdk_jacinto_08_02_00_21 |
NA |
NA |
NA |
NA |
FAIL*(4) |
Please check the mail and help to solve this issue in 1-2 Days.
Thanks very much.
Regards,
Jay
Hi Jay,
I took a brief look at this issue and seems like there is an issue with the interrupt registration for the MCAN ISR. I can see the MCAN_IR getting set properly by this is not translating to a core's interrupt because the interrupt is not correctly registered.
I will try to provide a working example on the EVM which you can refer.
Regards
Karan
Hi Jay,
As per my previous response, the ISR registration for the MCU R5F is the issue.
You can use the attached mcan_test_modify.c and compare it with yours. With the changes on the interrupt configuration and changing code to do internal loopback, I was able to get the Tx interrupts.
Note, I change the mode to internal loopback because maybe some transceiver configuration was not taken care of in your code, and even with the ISR triggering the message was not able to get out on the bus.
Please refer to the attached file.
/******************************************************************************
* Copyright (c) 2018-2021 Texas Instruments Incorporated - http://www.ti.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
/**
* \file mcan_test.c
*
* \brief This file contains MCAN sample code.
*
* Targeted Functionality: Verifying the transmit and receive functionality
* of MCAN module.
*
* Operation: MCAN operational mode is set to CAN-FD. This test will need
* two MCAN ports.
*
* Supported SoCs: AM65XX, J721E, J7200,AM64x, TPR12, AWR294X
*
* Supported Platforms: am65xx_idk, j721e_evm, j7200_evm, am64x_evm, am64x_svb, tpr12_evm, awr294x_evm
*
*/
#include "mcan_test.h"
#include <ti/csl/csl_mcan.h>
#include <stdlib.h>
#if defined(SOC_AWR294X)
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ti/drv/mibspi/MIBSPI.h>
#include <ti/drv/mibspi/soc/MIBSPI_soc.h>
#include <ti/drv/edma/edma.h>
#endif
//#define BOARD_DIAG_MCAN_DEBUG 1 // 20220623 FL ADD for debug
//#define BOARD_DEBUG_MCAN 1
#define MCAN_DIAG_INTR_ENABLE 1
static int32_t App_mcanRegisterIsr(uint32_t mcanInstAddr);
MCAN_TxBufElement txMsg;
MCAN_RxBufElement rxMsg;
volatile uint32_t gMcanIsrIntr0Flag = 1U;
volatile uint32_t gMcanIsrIntr1Flag = 1U;
uint32_t expBoardDetect = 0;
uint32_t mcanMaxPorts = 0;
uint32_t startPort = 0;
uint32_t g_TX_count = 0; // 20220624FL
uint32_t g_RX_count = 0; // 20220624FL
#if defined(am65xx_idk)
BoardDiag_McanPortInfo_t gMcanDiagPortInfo[MCAN_MAX_PORTS] =
{{CSL_MCU_MCAN0_MSGMEM_RAM_BASE, 0, CSL_GIC0_INTR_MCU_MCAN0_BUS_MCANSS_MCAN_LVL_INT_0, CSL_GIC0_INTR_MCU_MCAN0_BUS_MCANSS_MCAN_LVL_INT_1, CSL_GIC0_INTR_MCU_MCAN0_BUS_MCANSS_EXT_TS_ROLLOVER_LVL_INT},
{CSL_MCU_MCAN1_MSGMEM_RAM_BASE, 1, CSL_GIC0_INTR_MCU_MCAN1_BUS_MCANSS_MCAN_LVL_INT_0, CSL_GIC0_INTR_MCU_MCAN1_BUS_MCANSS_MCAN_LVL_INT_1, CSL_GIC0_INTR_MCU_MCAN1_BUS_MCANSS_EXT_TS_ROLLOVER_LVL_INT}
};
#elif defined(j7200_evm)
BoardDiag_McanPortInfo_t gMcanDiagPortInfo[MCAN_MAX_PORTS_EXP] =
{{CSL_MCU_MCAN0_MSGMEM_RAM_BASE, 0, MCU_MCAN0_TX_INT_NUM, MCU_MCAN0_RX_INT_NUM, MCU_MCAN0_TS_INT_NUM},
{CSL_MCU_MCAN1_MSGMEM_RAM_BASE, 1, MCU_MCAN1_TX_INT_NUM, MCU_MCAN1_RX_INT_NUM, MCU_MCAN1_TS_INT_NUM},
{CSL_MCAN0_MSGMEM_RAM_BASE, 0, MAIN_MCAN0_TX_INT_NUM, MAIN_MCAN0_RX_INT_NUM, MAIN_MCAN0_TS_INT_NUM},
{CSL_MCAN3_MSGMEM_RAM_BASE, 3, MAIN_MCAN3_TX_INT_NUM, MAIN_MCAN3_RX_INT_NUM, MAIN_MCAN3_TS_INT_NUM},
{CSL_MCAN4_MSGMEM_RAM_BASE, 4, MAIN_MCAN4_TX_INT_NUM, MAIN_MCAN4_RX_INT_NUM, MAIN_MCAN4_TS_INT_NUM},
{CSL_MCAN5_MSGMEM_RAM_BASE, 5, MAIN_MCAN5_TX_INT_NUM, MAIN_MCAN5_RX_INT_NUM, MAIN_MCAN5_TS_INT_NUM},
{CSL_MCAN6_MSGMEM_RAM_BASE, 6, MAIN_MCAN6_TX_INT_NUM, MAIN_MCAN6_RX_INT_NUM, MAIN_MCAN6_TS_INT_NUM},
{CSL_MCAN7_MSGMEM_RAM_BASE, 7, MAIN_MCAN7_TX_INT_NUM, MAIN_MCAN7_RX_INT_NUM, MAIN_MCAN7_TS_INT_NUM},
{CSL_MCAN8_MSGMEM_RAM_BASE, 8, MAIN_MCAN8_TX_INT_NUM, MAIN_MCAN8_RX_INT_NUM, MAIN_MCAN8_TS_INT_NUM},
{CSL_MCAN10_MSGMEM_RAM_BASE, 10, MAIN_MCAN10_TX_INT_NUM, MAIN_MCAN10_RX_INT_NUM, MAIN_MCAN10_TS_INT_NUM}
};
#elif defined(SOC_AM64X)
BoardDiag_McanPortInfo_t gMcanDiagPortInfo[MCAN_MAX_PORTS] =
{{CSL_MCAN0_MSGMEM_RAM_BASE, 0, MAIN_MCAN0_TX_INT_NUM, MAIN_MCAN0_RX_INT_NUM, MAIN_MCAN0_TS_INT_NUM},
{CSL_MCAN1_MSGMEM_RAM_BASE, 1, MAIN_MCAN1_TX_INT_NUM, MAIN_MCAN1_RX_INT_NUM, MAIN_MCAN1_TS_INT_NUM},
};
#elif (defined(tpr12_evm) || defined(awr294x_evm))
BoardDiag_McanPortInfo_t gMcanDiagPortInfo[MCAN_MAX_PORTS] = {{CSL_MSS_MCANA_MSG_RAM_U_BASE, 0, MAIN_MCAN0_TX_INT_NUM, MAIN_MCAN0_RX_INT_NUM, MAIN_MCAN0_TS_INT_NUM},
{CSL_MSS_MCANB_MSG_RAM_U_BASE, 1, MAIN_MCAN1_TX_INT_NUM, MAIN_MCAN1_RX_INT_NUM, MAIN_MCAN1_TS_INT_NUM},
};
#else
BoardDiag_McanPortInfo_t gMcanDiagPortInfo[MCAN_MAX_PORTS_EXP] =
{{CSL_MCU_MCAN0_MSGMEM_RAM_BASE, 0, MCU_MCAN0_TX_INT_NUM, MCU_MCAN0_RX_INT_NUM, MCU_MCAN0_TS_INT_NUM},
{CSL_MCU_MCAN1_MSGMEM_RAM_BASE, 1, MCU_MCAN1_TX_INT_NUM, MCU_MCAN1_RX_INT_NUM, MCU_MCAN1_TS_INT_NUM},
{CSL_MCAN0_MSGMEM_RAM_BASE, 0, MAIN_MCAN0_TX_INT_NUM, MAIN_MCAN0_RX_INT_NUM, MAIN_MCAN0_TS_INT_NUM},
{CSL_MCAN2_MSGMEM_RAM_BASE, 2, MAIN_MCAN2_TX_INT_NUM, MAIN_MCAN2_RX_INT_NUM, MAIN_MCAN2_TS_INT_NUM},
{CSL_MCAN4_MSGMEM_RAM_BASE, 4, MAIN_MCAN4_TX_INT_NUM, MAIN_MCAN4_RX_INT_NUM, MAIN_MCAN4_TS_INT_NUM},
{CSL_MCAN5_MSGMEM_RAM_BASE, 5, MAIN_MCAN5_TX_INT_NUM, MAIN_MCAN5_RX_INT_NUM, MAIN_MCAN5_TS_INT_NUM},
{CSL_MCAN6_MSGMEM_RAM_BASE, 6, MAIN_MCAN6_TX_INT_NUM, MAIN_MCAN6_RX_INT_NUM, MAIN_MCAN6_TS_INT_NUM},
{CSL_MCAN7_MSGMEM_RAM_BASE, 7, MAIN_MCAN7_TX_INT_NUM, MAIN_MCAN7_RX_INT_NUM, MAIN_MCAN7_TS_INT_NUM},
{CSL_MCAN9_MSGMEM_RAM_BASE, 9, MAIN_MCAN9_TX_INT_NUM, MAIN_MCAN9_RX_INT_NUM, MAIN_MCAN9_TS_INT_NUM},
{CSL_MCAN11_MSGMEM_RAM_BASE, 11, MAIN_MCAN11_TX_INT_NUM, MAIN_MCAN11_RX_INT_NUM, MAIN_MCAN11_TS_INT_NUM}
};
#endif
#if defined (SOC_J721E) || defined (SOC_J7200)
#define APP_MCU_MCAN_0_INT0 (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MCU_MCAN_0_INT1 (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MCU_MCAN_0_TS_INT (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MCU_MCAN_1_INT0 (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_MCAN_LVL_INT_0)
#define APP_MCU_MCAN_1_INT1 (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_MCAN_LVL_INT_1)
#define APP_MCU_MCAN_1_TS_INT (CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#if defined (SOC_J721E)
#if defined (BUILD_MCU1_0)
#define APP_MAIN_MCAN_2_INT0 (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0 + 28U)
#define APP_MAIN_MCAN_2_INT1 (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1 + 29U)
#define APP_MAIN_MCAN_2_TS_INT (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_2 + 30U)
#else
#define APP_MAIN_MCAN_0_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_0_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_0_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_2_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_2_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_4_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_4_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_5_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_5_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_6_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_6_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_7_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_7_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_9_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_9_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT0 (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0)
#define APP_MAIN_MCAN_11_INT1 (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1)
#define APP_MAIN_MCAN_11_TS_INT (CSLR_R5FSS1_CORE0_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0)
#endif
#endif
#if defined(SOC_AWR294X)
extern GPIO_v2_Config GPIO_v2_config;
EDMA_Handle gDmaHandle;
/**
* \brief Function to read PMIC register
*
* \param handle [IN] - SPI Handle
* \param regOffset [IN] - Register offset
*
* \return uint8_t Register Value
*
*/
static uint8_t BoardDiag_mcanReadPmicReg(MIBSPI_Handle handle, uint8_t regOffset)
{
uint8_t tx[4];
uint8_t rx[4];
MIBSPI_Transaction transaction;
memset(&transaction, 0, sizeof(transaction));
/* Configure Data Transfer */
transaction.count = 3;
transaction.txBuf = tx;
transaction.rxBuf = rx;
transaction.slaveIndex = 0;
tx[0] = regOffset;
tx[1] = 0x10;
tx[2] = 0;
/* Start Data Transfer */
MIBSPI_transfer(handle, &transaction);
return rx[2];
}
/**
* \brief Function to write PMIC register
*
* \param handle [IN] - SPI Handle
* \param regAddr [IN] - Register Address
* \param val [IN] - Register Value
*
*/
static void BoardDiag_mcanWritePmicReg(MIBSPI_Handle handle, uint8_t regAddr, uint8_t val)
{
uint8_t tx[4];
MIBSPI_Transaction transaction;
memset(&transaction, 0, sizeof(transaction));
/* Configure Data Transfer */
transaction.count = 3;
transaction.txBuf = tx;
transaction.rxBuf = NULL;
transaction.slaveIndex = 0;
tx[0] = regAddr;
tx[1] = 0;
tx[2] = val;
CacheP_wbInv((void *) tx, 3);
/* Start Data Transfer */
MIBSPI_transfer(handle, &transaction);
}
/**
* \brief Function to open edma
*
* \param devInstance [IN] - SPI Instance
*
*/
static int32_t BoardDiag_mcanEdmaOpen(uint8_t devInstance)
{
EDMA_instanceInfo_t instanceInfo;
int32_t errorCode;
MibSpi_HwCfg cfg;
int32_t retVal = 0;
retVal = MIBSPI_socGetInitCfg((enum MibSpi_InstanceId)devInstance, &cfg);
gDmaHandle = EDMA_getHandle(cfg.edmaCCId, &instanceInfo);
if(gDmaHandle == NULL)
{
EDMA3CCInitParams initParam;
EDMA3CCInitParams_init(&initParam);
initParam.initParamSet = TRUE;
if (EDMA_init(cfg.edmaCCId, &initParam) != EDMA_NO_ERROR)
{
printf("EDMA_init failed \n");
return -1;
}
/* Open DMA driver instance 0 for SPI test */
gDmaHandle = EDMA_open(cfg.edmaCCId, &errorCode, &instanceInfo);
}
if(gDmaHandle == NULL)
{
printf("Open DMA driver failed with error=%d\n", retVal);
return -1;
}
return 0;
}
/**
* \brief Function to configure CAN STB pin through PMIC
*
* \param devInstance [IN] - SPI Instance
*
*/
int32_t BoardDiag_mcanConfigSTB(uint8_t devInstance)
{
MIBSPI_Params params;
MIBSPI_Handle handle;
uint8_t regAddr;
uint8_t regValue;
if(BoardDiag_mcanEdmaOpen(devInstance))
{
UART_printf("DMA Open Failied\n");
return NULL;
}
/* Initialize the SPI */
MIBSPI_init();
/* Setup the default SPI Parameters */
MIBSPI_Params_init(¶ms);
/* Disble DMA */
params.dmaEnable = 1;
params.dmaHandle = gDmaHandle;
/* Set SPI in master mode */
params.mode = MIBSPI_MASTER;
params.u.masterParams.bitRate = 1000000U;
params.pinMode = MIBSPI_PINMODE_4PIN_CS;
params.dataSize = 8U;
params.frameFormat = MIBSPI_POL0_PHA1;
params.csHold = 1;
params.u.masterParams.numSlaves = 1U;
params.u.masterParams.t2cDelay = 0x5, /* t2cDelay */
params.u.masterParams.c2tDelay = 0x5, /* c2tDelay */
params.u.masterParams.wDelay = 0, /* wDelay */
params.u.masterParams.slaveProf[0].chipSelect = 0U;
params.u.masterParams.slaveProf[0].ramBufLen = MIBSPI_RAM_MAX_ELEM;
params.u.masterParams.slaveProf[0].dmaReqLine = 0U;
/* Open the SPI Instance for MibSpi */
handle = MIBSPI_open((enum MibSpi_InstanceId)devInstance, ¶ms);
regAddr = 0x3D;
regValue = BoardDiag_mcanReadPmicReg(handle, regAddr);
regValue = regValue | 0x1;
BOARD_delay(10000);
BoardDiag_mcanWritePmicReg(handle, regAddr, regValue);
regValue = BoardDiag_mcanReadPmicReg(handle, regAddr);
if((regValue & 0x1) != 0x1)
{
MIBSPI_close(handle);
return -1;
}
MIBSPI_close(handle);
return 0;
}
#endif
/* Macros used by test pattern generate function */
#define BOARD_DIAG_TEST_PATTERN_FF (0xFF)
#define BOARD_DIAG_TEST_PATTERN_AA (0xAA)
#define BOARD_DIAG_TEST_PATTERN_55 (0x55)
#define BOARD_DIAG_TEST_PATTERN_NULL (0)
#define BOARD_DIAG_TEST_PATTERN_RANDOM (1)
#define BOARD_DIAG_TEST_PATTERN_INC (2)
#define BOARD_DIAG_TEST_PATTERN_AA_55 (3)
/**
* \brief Generate test pattern function
*
* This function fills the data buffer passed as input parameter with
* different test patterns as indicated by 'flag' parameter.
* Below are the different test patterns supported
*
* BOARD_DIAG_TEST_PATTERN_FF - Fills the buffer with 0xFF
* BOARD_DIAG_TEST_PATTERN_AA - Fills the buffer with 0xAA
* BOARD_DIAG_TEST_PATTERN_55 - Fills the buffer with 0x55
* BOARD_DIAG_TEST_PATTERN_NULL - Fills buffer with 0
* BOARD_DIAG_TEST_PATTERN_RANDOM - Fills the buffer with randon pattern
* BOARD_DIAG_TEST_PATTERN_INC - Fills the buffer with increment pattern
* starting from 0
* BOARD_DIAG_TEST_PATTERN_AA_55 - Fills the buffer with 0xAA in even locations
* 0x55 in odd locations
*
* If 'flag' does match with any of the above values, buffer will be filled
* with 0 by default.
*
* \param buf [IN] Buffer to fill with the test pattern
* \param length [IN] Length of the buffer
* \param flag [IN] Flag to set the test pattern
*
*/
static void BoardDiag_genPattern(uint8_t *buf, uint32_t length, uint8_t flag)
{
uint8_t data = 0;
uint8_t incFlag = 0;
uint8_t randFlag = 0;
uint8_t checkerBoard = 0;
uint32_t idx;
switch(flag)
{
case BOARD_DIAG_TEST_PATTERN_FF:
case BOARD_DIAG_TEST_PATTERN_AA:
case BOARD_DIAG_TEST_PATTERN_55:
case BOARD_DIAG_TEST_PATTERN_NULL:
data = flag;
break;
case BOARD_DIAG_TEST_PATTERN_INC:
data = 0;
incFlag = 1;
break;
case BOARD_DIAG_TEST_PATTERN_RANDOM:
data = rand();
randFlag = 1;
case BOARD_DIAG_TEST_PATTERN_AA_55:
data = 0xAA;
checkerBoard = 1;
break;
default:
data = flag;
break;
}
for(idx = 0; idx < length; idx++)
{
buf[idx] = data;
if(incFlag)
data++;
if(randFlag)
data = rand();
if(checkerBoard)
data = ~data;
}
}
/**
* \brief This function will configure MCAN module
*
* \param index [IN] - MCAN index number
*
* \return int8_t
* 0 - in case of success
* -1 - in case of failure
*
*/
static int8_t BoardDiag_mcanConfig(uint8_t index)
{
uint32_t fdoe;
uint32_t baseAddr;
MCAN_RevisionId revId;
MCAN_InitParams initParams;
MCAN_ConfigParams configParams;
MCAN_MsgRAMConfigParams msgRAMConfigParams;
MCAN_StdMsgIDFilterElement stdFiltelem;
MCAN_BitTimingParams bitTimes;
/* Set base address */
baseAddr = gMcanDiagPortInfo[index].mcanBaseAddr;
/* Initialize MCAN Init params */
initParams.fdMode = 0x1U;
initParams.brsEnable = 0x1U;
initParams.txpEnable = 0x0U;
initParams.efbi = 0x0U;
initParams.pxhddisable = 0x0U;
initParams.darEnable = 0x1U;
initParams.wkupReqEnable = 0x1U;
initParams.autoWkupEnable = 0x1U;
initParams.emulationEnable = 0x1U;
initParams.emulationFAck = 0x0U;
initParams.clkStopFAck = 0x0U;
initParams.wdcPreload = 0xFFU;
initParams.tdcEnable = 0x1U;
initParams.tdcConfig.tdcf = 0xAU;
initParams.tdcConfig.tdco = 0x6U;
/* Initialize MCAN Config params */
configParams.monEnable = 0x0U;
configParams.asmEnable = 0x0U;
configParams.tsPrescalar = 0xFU;
configParams.tsSelect = 0x0U;
configParams.timeoutSelect = MCAN_TIMEOUT_SELECT_CONT;
configParams.timeoutPreload = 0xFFFFU;
configParams.timeoutCntEnable = 0x0U;
configParams.filterConfig.rrfs = 0x1U;
configParams.filterConfig.rrfe = 0x1U;
configParams.filterConfig.anfe = 0x1U;
configParams.filterConfig.anfs = 0x1U;
/* Initialize Message RAM Sections Configuration Parameters */
msgRAMConfigParams.flssa = APP_MCAN_STD_ID_FILT_START_ADDR;
msgRAMConfigParams.lss = APP_MCAN_STD_ID_FILTER_NUM;
msgRAMConfigParams.flesa = APP_MCAN_EXT_ID_FILT_START_ADDR;
msgRAMConfigParams.lse = APP_MCAN_EXT_ID_FILTER_NUM;
msgRAMConfigParams.txStartAddr = APP_MCAN_TX_BUFF_START_ADDR;
msgRAMConfigParams.txBufNum = APP_MCAN_TX_BUFF_SIZE;
msgRAMConfigParams.txFIFOSize = 0U;
msgRAMConfigParams.txBufMode = 0U;
msgRAMConfigParams.txBufElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
msgRAMConfigParams.txEventFIFOSize = APP_MCAN_TX_BUFF_SIZE;
msgRAMConfigParams.txEventFIFOWaterMark = 3U;
msgRAMConfigParams.rxFIFO0startAddr = APP_MCAN_FIFO_0_START_ADDR;
msgRAMConfigParams.rxFIFO0size = APP_MCAN_FIFO_0_NUM;
msgRAMConfigParams.rxFIFO0waterMark = 3U;
msgRAMConfigParams.rxFIFO0OpMode = 0U;
msgRAMConfigParams.rxFIFO1startAddr = APP_MCAN_FIFO_1_START_ADDR;
msgRAMConfigParams.rxFIFO1size = APP_MCAN_FIFO_1_NUM;
msgRAMConfigParams.rxFIFO1waterMark = 3U;
msgRAMConfigParams.rxFIFO1OpMode = 0U;
msgRAMConfigParams.rxBufStartAddr = APP_MCAN_RX_BUFF_START_ADDR;
msgRAMConfigParams.rxBufElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams.rxFIFO0ElemSize = MCAN_ELEM_SIZE_64BYTES;
msgRAMConfigParams.rxFIFO1ElemSize = MCAN_ELEM_SIZE_64BYTES;
/* Initialize Tx Buffer Config params */
stdFiltelem.sfid2 = 0x0U;
stdFiltelem.sfid1 = 0x4U;
stdFiltelem.sfec = 0x7U;
stdFiltelem.sft = 0x0U;
/* Initialize bit timings
* Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
bitTimes.nomRatePrescalar = 0x7U;
bitTimes.nomTimeSeg1 = 0x5U;
bitTimes.nomTimeSeg2 = 0x2U;
bitTimes.nomSynchJumpWidth = 0x0U;
bitTimes.dataRatePrescalar = 0x1U;
bitTimes.dataTimeSeg1 = 0x3U;
bitTimes.dataTimeSeg2 = 0x2U;
bitTimes.dataSynchJumpWidth = 0x0U;
/* Get MCANSS Revision ID */
MCAN_getRevisionId(baseAddr, &revId);
UART_printf("MCANSS Revision ID:\n");
UART_printf("scheme:0x%x\n",revId.scheme);
UART_printf("Business Unit:0x%x\n",revId.bu);
UART_printf("Module ID:0x%x\n",revId.modId);
UART_printf("RTL Revision:0x%x\n",revId.rtlRev);
UART_printf("Major Revision:0x%x\n",revId.major);
UART_printf("Custom Revision:0x%x\n",revId.custom);
UART_printf("Minor Revision:0x%x\n",revId.minor);
/* Enable Auto wakeup */
fdoe = MCAN_isFDOpEnable(baseAddr);
if ((uint32_t)TRUE == fdoe)
{
UART_printf("CAN-FD operation is enabled through E-Fuse.\n");
}
else
{
UART_printf("CAN-FD operation is disabled through E-Fuse.\n");
}
/* wait for memory initialization to happen */
while (FALSE == MCAN_isMemInitDone(baseAddr))
{}
/* Get endianess value */
UART_printf("Endianess Value:0x%x\n",MCAN_getEndianVal(baseAddr));
/* Put MCAN in SW initialization mode */
MCAN_setOpMode(baseAddr, MCAN_OPERATION_MODE_SW_INIT);
while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(baseAddr))
{}
/* Initialize MCAN module */
MCAN_init(baseAddr, &initParams);
/* Configure MCAN module */
MCAN_config(baseAddr, &configParams);
/* Configure Bit timings */
MCAN_setBitTime(baseAddr, &bitTimes);
/* Set Extended ID Mask */
MCAN_setExtIDAndMask(baseAddr, APP_MCAN_EXT_ID_AND_MASK);
/* Configure Message RAM Sections */
MCAN_msgRAMConfig(baseAddr, &msgRAMConfigParams);
/* Configure Standard ID filter element */
MCAN_addStdMsgIDFilter(baseAddr, 0U, &stdFiltelem);
/* Internal loopback mode */
MCAN_lpbkModeEnable (baseAddr, MCAN_LPBK_MODE_INTERNAL, TRUE);
/* Take MCAN out of the SW initialization mode */
MCAN_setOpMode(baseAddr, MCAN_OPERATION_MODE_NORMAL);
while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(baseAddr))
{}
return 0;
}
#if defined(MCAN_DIAG_INTR_ENABLE)
/**
* \brief This API will disable the TX and RX interrupts
*
* \param baseAddr [IN] MCAN base address
*
*/
static void BoardDiag_mcanTxIntDisable(uint32_t baseAddr)
{
/* Disable Interrupts */
MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)FALSE);
MCAN_enableIntr(baseAddr,
MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
/* Select Interrupt Line */
MCAN_selectIntrLine(baseAddr,
MCAN_INTR_MASK_ALL,
MCAN_INTR_LINE_NUM_0);
/* Disable Interrupt Line */
MCAN_enableIntrLine(baseAddr,
MCAN_INTR_LINE_NUM_0,
0U);
}
/**
* \brief This API will disable the RX interrupts
*
* \param baseAddr [IN] MCAN base address
*
*/
static void BoardDiag_mcanRxIntDisable(uint32_t baseAddr)
{
/* Disable Interrupts */
MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)FALSE);
MCAN_enableIntr(baseAddr,
MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
/* Select Interrupt Line */
MCAN_selectIntrLine(baseAddr,
MCAN_INTR_MASK_ALL,
MCAN_INTR_LINE_NUM_1);
/* Disable Interrupt Line */
MCAN_enableIntrLine(baseAddr,
MCAN_INTR_LINE_NUM_1,
0U);
}
/**
* \brief This API will enables the RX interrupts
*
* \param baseAddr [IN] MCAN base address
*
*/
static void BoardDiag_mcanRxIntEnable(uint32_t baseAddr)
{
/* Enable Interrupts */
MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
MCAN_enableIntr(baseAddr,
MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
/* Select Interrupt Line */
MCAN_selectIntrLine(baseAddr,
MCAN_INTR_MASK_ALL,
MCAN_INTR_LINE_NUM_1);
/* Enable Interrupt Line */
MCAN_enableIntrLine(baseAddr,
MCAN_INTR_LINE_NUM_1,
1U);
}
/**
* \brief This API will enables the TX interrupts
*
* \param baseAddr [IN] MCAN base address
*
*/
static int32_t BoardDiag_mcanTxIntEnable(uint32_t baseAddr)
{
int32_t status = 0;
MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
MCAN_enableIntr(baseAddr,
MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
/* Select Interrupt Line */
MCAN_selectIntrLine(baseAddr,
MCAN_INTR_MASK_ALL,
MCAN_INTR_LINE_NUM_0);
/* Enable Interrupt Line */
MCAN_enableIntrLine(baseAddr,
MCAN_INTR_LINE_NUM_0,
1U);
/* Enable Transmission interrupt */
status = MCAN_txBufTransIntrEnable(baseAddr,
1U,
(uint32_t)TRUE);
return status;
}
/**
* \brief This is Interrupt Service Routine for MCAN Tx interrupt.
*
* \param handle [IN/OUT] mcasp info structure
*
*/
static void BoardDiag_mcanTxIntrISR(void *handle)
{
uint32_t intrStatus;
uint32_t baseAddrs;
BoardDiag_McanPortInfo_t *intrInfo;
g_TX_count++;
intrInfo = (BoardDiag_McanPortInfo_t *)handle;
baseAddrs = intrInfo -> mcanBaseAddr;
intrStatus = MCAN_getIntrStatus(baseAddrs);
MCAN_clearIntrStatus(baseAddrs, intrStatus);
if (MCAN_INTR_SRC_TRANS_COMPLETE ==
(intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
{
gMcanIsrIntr0Flag = 0U;
}
}
/**
* \brief This is Interrupt Service Routine for MCAN Rx interrupt.
*
* \param handle [IN/OUT] mcasp info structure
*
*/
static void BoardDiag_mcanRxIntrISR(void *handle)
{
uint32_t intrStatus;
uint32_t baseAddrs;
BoardDiag_McanPortInfo_t *intrInfo;
g_RX_count++;
intrInfo = (BoardDiag_McanPortInfo_t *)handle;
baseAddrs = intrInfo -> mcanBaseAddr;
intrStatus = MCAN_getIntrStatus(baseAddrs);
MCAN_clearIntrStatus(baseAddrs, intrStatus);
if (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG ==
(intrStatus & MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
{
gMcanIsrIntr1Flag = 0U;
}
}
/**
* \brief This function will configure MCAN Tx interrupts
*
* \param index [IN] - MCAN index number
*
*/
#if 0
static void BoardDiag_mcanTxIntrConfig(uint32_t index)
{
#if !defined(SOC_AM64X)
#if defined (__aarch64__)
Intc_Init(index);
/* Enable CPU Interrupts and register ISR - MCAN Intr0 */
Intc_IntRegister(gMcanDiagPortInfo[index].mcanTxIntNum,
(IntrFuncPtr) BoardDiag_mcanTxIntrISR, (void*)(&gMcanDiagPortInfo[index]));
Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTxIntNum, 1U, 0U);
Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTxIntNum);
//Intc_SystemEnable();
UART_printf("Tx Interrupt Configuration done.\n");
#endif
#else
#if !defined (__aarch64__)
Intc_Init(0);
/* Enable CPU Interrupts and register ISR - MCAN Intr0 */
Intc_IntRegister(gMcanDiagPortInfo[index].mcanTxIntNum,
(IntrFuncPtr) BoardDiag_mcanTxIntrISR, (void*)(&gmcanDiagportInfo[index]));
Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTxIntNum, 1U, 0U);
Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTxIntNum);
UART_printf("Tx Interrupt Configuration done.\n");
#endif
#endif
}
#endif
/**
* \brief This function will configure MCAN Rx interrupts
*
* \param index [IN] - MCAN index number
*
*/
static void BoardDiag_mcanRxIntrConfig(uint32_t index)
{
#if !defined(SOC_AM64X)
#if defined (__aarch64__)
Intc_Init(0);
/* Enable CPU Interrupts and register ISR - MCAN Intr0 */
Intc_IntRegister(gMcanDiagPortInfo[index].mcanRxIntNum,
(IntrFuncPtr) BoardDiag_mcanRxIntrISR, (void*)(&gMcanDiagPortInfo[index]));
Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanRxIntNum, 1U, 0U);
Intc_SystemEnable(gMcanDiagPortInfo[index].mcanRxIntNum);
UART_printf("Rx Interrupt Configuration done.\n");
#endif
#else
#if !defined (__aarch64__)
Intc_Init(0);
/* Enable CPU Interrupts and register ISR - MCAN Intr0 */
Intc_IntRegister(gMcanDiagPortInfo[index].mcanRxIntNum,
(IntrFuncPtr) BoardDiag_mcanRxIntrISR, (void*)(&gmcanDiagportInfo[index]));
Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanRxIntNum, 1U, 0U);
Intc_SystemEnable(gMcanDiagPortInfo[index].mcanRxIntNum);
UART_printf("Rx Interrupt Configuration done.\n");
#endif
#endif
}
#if defined(MCAN_DIAG_TS_INT_ENABLE)
/**
* \brief This is Interrupt Service Routine for MCAN TimeStamp interrupt.
*
* \param handle [IN/OUT] mcasp info structure
*
*/
static void BoardDiag_mcanTsIntrISR(void *handle)
{
uint32_t baseAddrs;
BoardDiag_McanPortInfo_t *intrInfo;
intrInfo = (BoardDiag_McanPortInfo_t *)handle;
baseAddrs = intrInfo -> mcanBaseAddr;
if(MCAN_extTSIsIntrEnable(baseAddrs) == (uint32_t)TRUE)
{
UART_printf("MCAN Time Stamp overflow happened.\n");
}
MCAN_extTSClearRawStatus(baseAddrs);
MCAN_extTSWriteEOI(baseAddrs);
}
/**
* \brief This function will configure MCAN Rx interrupts
*
* \param index [IN] - MCAN index number
*
*/
static void BoardDiag_mcanTsIntrConfig(uint32_t index)
{
#if !defined(SOC_AM64X)
#if defined (__aarch64__)
Intc_Init(0);
/* Enable CPU Interrupts and register ISR - MCAN Intr0 */
Intc_IntRegister(gMcanDiagPortInfo[index].mcanTsIntNum,
(IntrFuncPtr) BoardDiag_mcanTsIntrISR, (void*)(&gMcanDiagPortInfo[index]));
Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTsIntNum, 1U, 0U);
Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTsIntNum);
UART_printf("Tx Interrupt Configuration done.\n");
#endif
#else
#if !defined (__aarch64__)
Intc_Init(0);
/* Enable CPU Interrupts and register ISR - MCAN Intr0 */
Intc_IntRegister(gMcanDiagPortInfo[index].mcanTsIntNum,
(IntrFuncPtr) BoardDiag_mcanTsIntrISR, (void*)(&gmcanDiagportInfo[index]));
Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTsIntNum, 1U, 0U);
Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTsIntNum);
UART_printf("Tx Interrupt Configuration done.\n");
#endif
#endif
}
#endif /* #if defined(MCAN_DIAG_TS_INT_ENABLE) */
#endif /* #if defined(MCAN_DIAG_INTR_ENABLE) */
#if defined(BOARD_DIAG_MCAN_DEBUG)
/**
* \brief This API will print MCAN Tx Msg.
*
*/
static void BoardDiag_mcanPrintTxMsg(void)
{
uint32_t loopCnt;
UART_printf("\nMessage ID:0x%x\n", txMsg.id);
UART_printf("\nMessage Remote Transmission Request:0x%x\n",txMsg.rtr);
UART_printf("\nMessage Extended Frame ID(0:11Bit ID/1:29bit ID):0x%x\n",
txMsg.xtd);
UART_printf("\nMessage Error State Indicator(0:Error Active/1:Error Passive):0x%x\n",txMsg.esi);
UART_printf("\nMessage Data Length Code:0x%x\n",txMsg.dlc);
UART_printf("\nMessage BRS:0x%x\n",txMsg.brs);
UART_printf("\nMessage CAN FD format:0x%x\n",txMsg.fdf);
UART_printf("\nMessage Store Tx Events:0x%x\n",txMsg.efc);
UART_printf("\nMessage Marker:0x%x\n",txMsg.mm);
for (loopCnt = 0U; loopCnt < txMsg.dlc; loopCnt++)
{
UART_printf("\nMessage DataByte%d:0x%x\n",loopCnt,txMsg.data[loopCnt]);
}
}
/**
* \brief This API will print MCAN Rx Msg.
*
*/
static void BoardDiag_mcanPrintRxMsg(void)
{
uint32_t loopCnt;
UART_printf("\nReceived last message with following details:");
UART_printf("\nMessage ID:0x%x\n",rxMsg.id);
UART_printf("\nMessage Remote Transmission Request:0x%x\n",rxMsg.rtr);
UART_printf("\nMessage Extended Frame ID(0:11Bit ID/1:29bit ID):0x%x\n",
rxMsg.xtd);
UART_printf("\nMessage Error State Indicator(0:Error Active/1:Error Passive):0x%x\n", rxMsg.esi);
UART_printf("\nMessage TimeStamp:0x%x\n",rxMsg.rxts);
UART_printf("\nMessage Data Length Code:0x%x\n",rxMsg.dlc);
UART_printf("\nMessage BRS:0x%x\n",rxMsg.brs);
UART_printf("\nMessage CAN FD format:0x%x\n",rxMsg.fdf);
UART_printf("\nMessage Filter Index:0x%x\n",rxMsg.fidx);
UART_printf("\nMessage Accept Non-matching Frame:0x%x\n",rxMsg.anmf);
for (loopCnt = 0U; loopCnt < rxMsg.dlc; loopCnt++)
{
UART_printf("\nMessage DataByte%d:0x%x\n",loopCnt,rxMsg.data[loopCnt]);
}
}
#endif /* #if defined(BOARD_DIAG_MCAN_DEBUG) */
/**
* \brief This API will load the data to the message ram and checking
* the error status
*
* \param instance [IN] - MCAN instance number
*
* \return int8_t
* 0 - in case of success
* -1 - in case of failure
*
*/
static int8_t BoardDiag_mcanTxTest(uint8_t instance)
{
int8_t configStatus = 0;
uint32_t baseAddr;
MCAN_ProtocolStatus protStatus;
/* Set base address */
baseAddr = gMcanDiagPortInfo[instance].mcanBaseAddr;
#if defined(MCAN_DIAG_INTR_ENABLE)
#if 0
BoardDiag_mcanTxIntrConfig(instance);
#endif
configStatus = BoardDiag_mcanTxIntEnable(baseAddr);
#endif
/* Write message to Msg RAM */
MCAN_writeMsgRam(baseAddr,
MCAN_MEM_TYPE_BUF,
APP_MCAN_TX_BUF_NUM,
&txMsg);
/* Add request for transmission */
configStatus += MCAN_txBufAddReq(baseAddr, APP_MCAN_TX_BUF_NUM);
if (configStatus != 0)
{
UART_printf("\nError in Adding Transmission Request...\n");
return -1;
}
#if defined(MCAN_DIAG_INTR_ENABLE)
UART_printf("\n 1. TX:CAN ISR row stats: %x, %x, %x, %x \n",HW_RD_REG32(0x40528050), HW_RD_REG32(0x40528054), HW_RD_REG32(0x40528058), HW_RD_REG32(0x4052805C) );
UART_printf("\n 2. TX:CAN ISR row stats: %x, %x, %x, %x \n",MCAN_getIntrStatus(baseAddr), HW_RD_REG32(0x40528054), MCAN_getIntrLineSelectStatus(baseAddr), HW_RD_REG32(0x4052805C) );
UART_printf("\n 3. TX:CAN ISR row stats: %x, %x, %x, %x \n",HW_RD_REG32(0x40528050), HW_RD_REG32(0x40528054), HW_RD_REG32(0x40528058), HW_RD_REG32(0x4052805C) );
while (gMcanIsrIntr0Flag)
{
UART_printf("intr:0x%x, g_TX_count=%d \n",MCAN_getIntrStatus(baseAddr), g_TX_count);
}
gMcanIsrIntr0Flag = 1U;
#else
/* Waiting for Transmission Complete */
while(((MCAN_getTxBufReqPend(baseAddr) >>
APP_MCAN_TX_BUF_NUM) & 0x1) == 0x1);
#endif
MCAN_getProtocolStatus(baseAddr, &protStatus);
/* Checking for Errors */
if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
(MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
(MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
(0U == protStatus.pxe))
{
UART_printf("Message successfully transferred with payload Bytes:0x%x\n",txMsg.dlc);
}
else
{
UART_printf("Error in transmission with payload Bytes:0x%x\n", txMsg.dlc);
configStatus = -1;
}
return configStatus;
}
/**
* \brief This API will receive the data and compares with the transmit data
*
* \param instance [IN] - MCAN instance number
*
* \return int8_t
* 0 - in case of success
* -1 - in case of failure
*
*/
static int8_t BoardDiag_mcanRxTest(uint8_t index)
{
uint32_t chkCnt = 0U;
uint32_t errFlag = 0U;
uint32_t baseAddr;
int8_t testStatus = 0;
MCAN_RxNewDataStatus newDataStatus;
MCAN_ErrCntStatus errCounter;
/* Set base address */
baseAddr = gMcanDiagPortInfo[index].mcanBaseAddr;
#if defined(MCAN_DIAG_INTR_ENABLE)
BoardDiag_mcanRxIntrConfig(index);
BoardDiag_mcanRxIntEnable(baseAddr);
#endif
#if defined(MCAN_DIAG_INTR_ENABLE)
UART_printf("\n 1. RX:CAN ISR row stats: %x, %x, %x, %x \n",HW_RD_REG32(0x40528050), HW_RD_REG32(0x40528054), HW_RD_REG32(0x40528058), HW_RD_REG32(0x4052805C) );
UART_printf("\n 2. RX:CAN ISR row stats: %x, %x, %x, %x \n",MCAN_getIntrStatus(baseAddr), HW_RD_REG32(0x40528054), MCAN_getIntrLineSelectStatus(baseAddr), HW_RD_REG32(0x4052805C) );
UART_printf("\n 3. RX:CAN ISR row stats: %x, %x, %x, %x \n",HW_RD_REG32(0x40528050), HW_RD_REG32(0x40528054), HW_RD_REG32(0x40528058), HW_RD_REG32(0x4052805C) );
while (gMcanIsrIntr1Flag)
{
UART_printf("intr:0x%x, g_RX_count=%d \n",MCAN_getIntrStatus(baseAddr), g_RX_count);
}
gMcanIsrIntr1Flag = 1U;
#else
/* Waiting for Transmission Complete */
UART_printf("\n MCAN_getIntrStatus(baseAddr) 0x%x\n", MCAN_getIntrStatus(baseAddr));
UART_printf("\n MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG) = 0x%x\n", MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG);
while(MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG !=
(MCAN_getIntrStatus(baseAddr) &
MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG));
UART_printf("\n MCAN_getIntrStatus have MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG\n");
#endif
/* Checking for Errors */
MCAN_getErrCounters(baseAddr, &errCounter);
if ((0U == errCounter.recErrCnt) &&
(0U == errCounter.canErrLogCnt))
{
MCAN_getNewDataStatus(baseAddr, &newDataStatus);
MCAN_clearNewDataStatus(baseAddr, &newDataStatus);
MCAN_readMsgRam(baseAddr,
MCAN_MEM_TYPE_BUF,
0U,
0U,
&rxMsg);
errFlag = 0U;
for (chkCnt = 0U; chkCnt < rxMsg.dlc; chkCnt++)
{
if (txMsg.data[chkCnt] != rxMsg.data[chkCnt])
{
errFlag = 1U;
break;
}
}
if (0U == errFlag)
{
UART_printf("\nMessage successfully received with payload Bytes:0x%x\n",rxMsg.dlc);
}
else
{
UART_printf("\nWrong data received in message with payload Bytes:0x%x\n",rxMsg.dlc);
testStatus = -1;
}
}
else
{
UART_printf("\nError in reception with payload Bytes:0x%x\n", txMsg.dlc);
testStatus = -1;
}
#if defined(BOARD_DIAG_MCAN_DEBUG)
BoardDiag_mcanPrintRxMsg();
#endif
return testStatus;
}
#if defined(SOC_J721E) || defined(SOC_J7200)
/**
* \brief This function enables the Main CAN module and transceiver by setting
* the Enable and STB Pins
*
*/
static void BoardDiag_mcanMainconfigs(void)
{
MCAN_lpbkModeEnable(gMcanDiagPortInfo[0].mcanBaseAddr, MCAN_LPBK_MODE_INTERNAL, TRUE);
#if 0
Board_IoExpCfg_t ioExpCfg;
Board_STATUS status = BOARD_SOK;
ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;
ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE2_ADDR;
ioExpCfg.enableIntr = false;
ioExpCfg.ioExpType = THREE_PORT_IOEXP;
ioExpCfg.portNum = PORTNUM_0;
ioExpCfg.pinNum = PIN_NUM_6;
ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);
if(status != BOARD_SOK)
{
UART_printf("Failed to enable the main MCAN0 \n");
}
ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;
ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE2_ADDR;
ioExpCfg.enableIntr = false;
ioExpCfg.ioExpType = THREE_PORT_IOEXP;
ioExpCfg.portNum = PORTNUM_0;
ioExpCfg.pinNum = PIN_NUM_7;
ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);
if(status != BOARD_SOK)
{
UART_printf("Failed to set the mcan0 stb pin to normal mode\n");
}
#if defined(j721e_evm)
ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;
ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE2_ADDR;
ioExpCfg.enableIntr = false;
ioExpCfg.ioExpType = THREE_PORT_IOEXP;
ioExpCfg.portNum = PORTNUM_1;
ioExpCfg.pinNum = PIN_NUM_4;
ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;
status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);
if(status != BOARD_SOK)
{
UART_printf("Failed to enable the MCAN mux selection\n");
}
#endif
#endif
}
#endif /* #if defined(SOC_J721E) || defined(SOC_J7200) */
#if !defined(SOC_AM64X) && !defined(SOC_TPR12) && !defined(SOC_AWR294X)
/**
* \brief This API Initializes the GPIO module
*
* \param gpioBaseAddrs [IN] GPIO base address to configure
* \param port [IN] GPIO Port number
*
*/
static void BoardDiag_mcanGpioConfig(uint32_t gpioBaseAddrs,uint32_t port)
{
GPIO_v0_HwAttrs gpioCfg;
GPIO_socGetInitCfg(port, &gpioCfg);
gpioCfg.baseAddr = gpioBaseAddrs;
GPIO_socSetInitCfg(port, &gpioCfg);
/* GPIO initialization */
GPIO_init();
}
#endif
#if defined(j7200_evm)
/**
* \brief UART Mux enable function
*
* This function is used to enable the uart mux selection
*
* \param pinNum - I2C IO EXPANDER pin number
* \param pinVal - I2C IO EXPANDER pin value
*
*/
void BoardDiag_McanMuxEnable(i2cIoExpPinNumber_t pinNum,
i2cIoExpSignalLevel_t pinVal)
{
#if 0
Board_IoExpCfg_t ioExpCfg;
Board_STATUS status = BOARD_SOK;
/* Enable the UART1 and UART3 */
ioExpCfg.i2cInst = BOARD_I2C_IOEXP_SOM_DEVICE1_INSTANCE;
ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_SOM_DEVICE1_ADDR;
ioExpCfg.enableIntr = false;
ioExpCfg.ioExpType = ONE_PORT_IOEXP;
ioExpCfg.portNum = PORTNUM_0;
ioExpCfg.pinNum = pinNum;
ioExpCfg.signalLevel = pinVal;
status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);
if(status != BOARD_SOK)
{
UART_printf("Failed to select the MCAN Mux\n");
}
endif
#endif
}
#endif
#if !defined(SOC_TPR12) && !defined(SOC_AWR294X)
/**
* \brief This API enables the CAN transceivers by setting the STB pins
*
*/
static void BoardDiag_mcanEnable(void)
{
#if 0
#if defined(SOC_J721E) || defined(SOC_J7200)
Board_IoExpCfg_t ioExpCfg;
Board_STATUS status = BOARD_SOK;
#endif
#if defined (am65xx_idk)
BoardDiag_mcanGpioConfig(CSL_GPIO1_BASE, 1);
GPIO_write(0, 1);
GPIO_write(1, 1);
#elif defined(SOC_AM64X)
Board_I2cInitCfg_t i2cCfg;
i2cCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;
i2cCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
i2cCfg.enableIntr = false;
Board_setI2cInitConfig(&i2cCfg);
Board_i2cIoExpInit();
/* Setting the pin direction as output */
Board_i2cIoExpSetPinDirection(BOARD_I2C_IOEXP_DEVICE1_ADDR,
THREE_PORT_IOEXP,
PORTNUM_1,
PIN_NUM_0,
PIN_DIRECTION_OUTPUT);
/* Pulling the MCAN0_STB_EN pin to low for normal mode */
Board_i2cIoExpPinLevelSet(BOARD_I2C_IOEXP_DEVICE1_ADDR,
THREE_PORT_IOEXP,
PORTNUM_1,
PIN_NUM_0,
GPIO_SIGNAL_LEVEL_LOW);
/* Setting the pin direction as output */
Board_i2cIoExpSetPinDirection(BOARD_I2C_IOEXP_DEVICE1_ADDR,
THREE_PORT_IOEXP,
PORTNUM_1,
PIN_NUM_1,
PIN_DIRECTION_OUTPUT);
/* Pulling the MCAN1_STB_EN pin to low for normal mode */
Board_i2cIoExpPinLevelSet(BOARD_I2C_IOEXP_DEVICE1_ADDR,
THREE_PORT_IOEXP,
PORTNUM_1,
PIN_NUM_1,
GPIO_SIGNAL_LEVEL_LOW);
BOARD_delay(1000);
Board_i2cIoExpDeInit();
#else
BoardDiag_mcanGpioConfig(CSL_WKUP_GPIO0_BASE,0);
/* Enable MCU CAN transceivers by setting the STB pins */
GPIO_write(0, 1); /* MCU_CAN0_STB */
GPIO_write(1, 0); /* MCU_CAN1_STB */
/* MCU_MCAN0_EN */
GPIO_write(2, 1); /* WKUP_GPIO0_0 */
/* Enable CP board MAIN CAN transceivers by setting the STB pins */
//BoardDiag_mcanMainconfigs();
#if defined(j721e_evm)
/* MAIN CAN2 STB */
BoardDiag_mcanGpioConfig(CSL_GPIO0_BASE, 0);
GPIO_write(3, 0); /* GPIO0_127 */
#endif
if(expBoardDetect)
{
UART_printf("GESI board Detected\n");
ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;
ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE1_ADDR;
ioExpCfg.enableIntr = false;
ioExpCfg.ioExpType = TWO_PORT_IOEXP;
ioExpCfg.portNum = PORTNUM_1;
ioExpCfg.pinNum = PIN_NUM_4;
ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;
status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);
if(status != BOARD_SOK)
{
UART_printf("Failed to set the GESI board mcan stb pin to normal mode \n");
}
#if defined(j7200_evm)
/* Enable GESI CAN STB pin to normal mode */
BoardDiag_McanMuxEnable(PIN_NUM_7, GPIO_SIGNAL_LEVEL_LOW);
Board_control(BOARD_CTRL_CMD_SET_SOM_CAN_MUX, NULL);
#else
/* GPIO0_60 */
BoardDiag_mcanGpioConfig(CSL_GPIO0_BASE, 0);
GPIO_write(4, 0);
#endif
}
#endif
#endif
}
#endif /* #if !defined(SOC_TPR12) && !defined(SOC_AWR294X) */
/**
* \brief This function executes MCAN Diagnostic test
*
* \return int8_t
* 0 - in case of success
* -1 - in case of failure
*
*/
int32_t BoardDiag_mcanTest(void)
{
int8_t ret = 0;
uint32_t index;
uint32_t portNum;
int32_t configStatus = CSL_PASS;
#if defined(DIAG_STRESS_TEST) && (defined(am65xx_idk) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X))
char rdBuf = 'y';
#endif
#if defined(DIAG_STRESS_TEST) && ((defined(am65xx_idk)) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X))
UART_printf ("***********************************************\n");
UART_printf ("* MCAN Stress Test *\n");
UART_printf ("***********************************************\n");
#else
UART_printf ("***********************************************\n");
UART_printf ("* MCAN Test_FL *\n");
UART_printf ("***********************************************\n");
#endif
#if !defined(SOC_TPR12) && !defined(SOC_AWR294X)
BoardDiag_mcanEnable();
#endif
#if defined(am65xx_idk) || defined(SOC_AM64X) || defined(SOC_TPR12) || defined(SOC_AWR294X)
mcanMaxPorts = MCAN_MAX_PORTS;
#else
if(expBoardDetect)
{
mcanMaxPorts = MCAN_MAX_PORTS_EXP;
}
else
{
mcanMaxPorts = MCAN_MAX_PORTS_CP;
}
#endif
configStatus = App_mcanRegisterIsr(CSL_MCU_MCAN0_MSGMEM_RAM_BASE);
/* Initialize message to transmit */
txMsg.id = (uint32_t)((uint32_t)(0x41U) << 18U); // 20220623FL change ID to 0x41
txMsg.rtr = 0U;
txMsg.xtd = 0U;
txMsg.esi = 0U;
//txMsg.dlc = 0xFU;
txMsg.dlc = 0x8U; // 20220623FL change length to 8
txMsg.brs = 1U;
txMsg.fdf = 1U;
txMsg.efc = 1U;
txMsg.mm = 0xAAU;
for(portNum = 0; portNum < mcanMaxPorts; portNum += 2)
{
/* Configure MCAN */
ret = BoardDiag_mcanConfig(portNum);
if(ret == 0)
{
UART_printf("Successfully configured MCAN%d\n",portNum);
}
ret = BoardDiag_mcanConfig(portNum+1);
if(ret == 0)
{
UART_printf("Successfully configured MCAN%d\n",portNum+1);
}
//UART_printf("\n\nTransmitting Data on MCAN Port%d and Receiving on MCAN port%d\n",portNum, portNum+1);
UART_printf("\n Transmitting Data on MCAN Port%d Test \n",portNum);
for(index = 0; index < PKT_SEND_COUNT; index++)
{
UART_printf("\n Port %d Sending Packet - %d\n", portNum, (index + 1));
/* Fill the Tx buffer with random data */
BoardDiag_genPattern(txMsg.data, MCAN_MAX_PAYLOAD_BYTES,
BOARD_DIAG_TEST_PATTERN_RANDOM);
/* Transmiting port */
ret = BoardDiag_mcanTxTest(portNum);
if(ret != 0)
{
UART_printf("Failed to transmit data on port%d\n",portNum);
return (-1);
}
#if 0 // test CAN1
UART_printf("\n Port %d Sending Packet - %d\n", (portNum+1), (index + 1));
/* Fill the Tx buffer with random data */
BoardDiag_genPattern(txMsg.data, MCAN_MAX_PAYLOAD_BYTES,
BOARD_DIAG_TEST_PATTERN_RANDOM);
/* Transmiting port */
ret = BoardDiag_mcanTxTest(portNum+1);
if(ret != 0)
{
UART_printf("Failed to transmit data on port%d\n",portNum+1);
return (-1);
}
#endif
#if defined(BOARD_DEBUG_MCAN)
BoardDiag_mcanPrintTxMsg();
#endif
#if 0 // 20220623 FL remove receive part here.
/* Receiving port*/
ret = BoardDiag_mcanRxTest(portNum+1);
if(ret != 0)
{
UART_printf("Failed to receive data on port%d",portNum);
return (-1);
}
UART_printf("\nReceived Packet - %d\n\n", (index + 1));
#endif
#if defined(DIAG_STRESS_TEST) && ((defined(am65xx_idk)) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X))
/* Check if there a input from console to break the test */
rdBuf = (char)BoardDiag_getUserInput(BOARD_UART_INSTANCE);
if((rdBuf == 'b') || (rdBuf == 'B'))
{
UART_printf("Received Test Termination... Exiting the Test\n\n");
UART_printf("MCAN Stress Test Status\n");
UART_printf("============================================\n");
UART_printf("Total Number of Packets sent: %d\nTotal Number of Packets Received: %d\n",index + 1,index + 1);
break;
}
#endif
#if defined(MCAN_DIAG_INTR_ENABLE)
/* Disable the TX and RX interrupts */
//BoardDiag_mcanTxIntDisable(gMcanDiagPortInfo[portNum].mcanBaseAddr);
//BoardDiag_mcanRxIntDisable(gMcanDiagPortInfo[portNum+1].mcanBaseAddr);
#endif
}
// UART_printf("\n\nTransmitting Data on MCAN Port%d and Receiving on MCAN port%d\n",portNum+1, portNum);
UART_printf("\n Try Receiving on MCAN port%d\n",portNum);
for(index = 0; index < PKT_SEND_COUNT; index++)
{
#if 0 // 20220623 FL remove
UART_printf("\nSending Packet - %d\n", (index + 1));
/* Fill the Tx buffer with random data */
BoardDiag_genPattern(txMsg.data, MCAN_MAX_PAYLOAD_BYTES,
BOARD_DIAG_TEST_PATTERN_RANDOM);
/* Transmitting port*/
ret = BoardDiag_mcanTxTest(portNum+1);
if(ret != 0)
{
UART_printf("Failed to transmit data on port%d",portNum+1);
return -1;
}
#if defined(BOARD_DEBUG_MCAN)
BoardDiag_mcanPrintTxMsg();
UART_printf("Receiving data on port%d\n", portNum);
#endif
#endif
/* Receiving port */
ret = BoardDiag_mcanRxTest(portNum);
if(ret != 0)
{
UART_printf("Failed to receive data on port%d\n",portNum);
return (-1);
}
UART_printf("\nReceived Packet - %d\n\n", (index + 1));
#if defined(DIAG_STRESS_TEST) && ((defined(am65xx_idk)) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X))
/* Check if there a input from console to break the test */
rdBuf = (char)BoardDiag_getUserInput(BOARD_UART_INSTANCE);
if((rdBuf == 'b') || (rdBuf == 'B'))
{
UART_printf("Received Test Termination... Exiting the Test\n\n");
UART_printf("MCAN Stress Test Status\n");
UART_printf("============================================\n");
UART_printf("Total Number of Packets sent: %d\nTotal Number of Packets Received: %d\n",index + 1,index + 1);
break;
}
#endif
#if defined(MCAN_DIAG_INTR_ENABLE)
/* Disable the TX and RX interrupts */
BoardDiag_mcanTxIntDisable(gMcanDiagPortInfo[portNum+1].mcanBaseAddr);
BoardDiag_mcanRxIntDisable(gMcanDiagPortInfo[portNum+1].mcanBaseAddr);
#endif
}
}
UART_printf("\n MCAN diagnostic test completed.\n");
return 0;
}
/**
* \brief main function
*
* This function performs board initializations and calls MCAN test
*
* \return int
* 0 - in case of success
* -1 - in case of failure
*
*/
volatile uint32_t ccs_loop = 0xDEADBEEF;
int main(void)
{
while(ccs_loop);
int32_t retVal;
Board_STATUS status;
Board_initCfg boardCfg;
#if 0
#if defined(j721e_evm) || defined(j7200_evm)
if(Board_detectBoard(BOARD_ID_GESI) == TRUE)
{
expBoardDetect = 1;
}
#endif
#endif
expBoardDetect = 0;
#if defined(j721e_evm)
Board_PinmuxConfig_t gesiIcssgPinmux;
if(expBoardDetect)
{
Board_pinmuxGetCfg(&gesiIcssgPinmux);
gesiIcssgPinmux.autoCfg = BOARD_PINMUX_CUSTOM;
gesiIcssgPinmux.gesiExp = BOARD_PINMUX_GESI_ICSSG;
Board_pinmuxSetCfg(&gesiIcssgPinmux);
}
#endif
#ifdef PDK_RAW_BOOT
boardCfg = BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_PINMUX_CONFIG |
BOARD_INIT_UART_STDIO;
#else
boardCfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG ;
#endif
status = Board_init(boardCfg);
if(status != BOARD_SOK)
{
return -1;
}
#if defined(SOC_AWR294X)
/* Configure CAN Enable pin */
GPIO_v2_updateConfig(&GPIO_v2_config);
GPIO_init();
GPIO_write(GPIO_v2_config.pinConfigs[0].pinIndex, 1);
/* Configure CAN STB pin */
retVal = BoardDiag_mcanConfigSTB(MIBSPI_INST_ID_MSS_SPIB);
if(retVal != 0)
{
UART_printf("CAN STB Pin Configurations Failed!!\n");
return retVal;
}
else
{
UART_printf("CAN STB Pin Configurations Successful!\n");
}
#endif
retVal = BoardDiag_mcanTest();
return retVal;
}
uint32_t gMcanModAddr = CSL_MCU_MCAN0_MSGMEM_RAM_BASE;
static void App_mcanIntr0ISR(uintptr_t arg)
{
uint32_t intrStatus;
g_TX_count++;
intrStatus = MCAN_getIntrStatus(gMcanModAddr);
MCAN_clearIntrStatus(gMcanModAddr, intrStatus);
if (MCAN_INTR_SRC_TRANS_COMPLETE ==
(intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
{
gMcanIsrIntr0Flag = 0U;
}
if (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG ==
(intrStatus & MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
{
gMcanIsrIntr1Flag = 0U;
}
}
static void App_mcanIntr1ISR(uintptr_t arg)
{
uint32_t intrStatus;
intrStatus = MCAN_getIntrStatus(gMcanModAddr);
MCAN_clearIntrStatus(gMcanModAddr, intrStatus);
if (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG ==
(intrStatus & MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
{
gMcanIsrIntr1Flag = 0U;
}
}
static void App_mcanTSIntrISR(uintptr_t arg)
{
UART_printf("Time Stamp overflow happened.\n");
}
static int32_t App_mcanRegisterInterrupt(uint32_t intNum, void f(uintptr_t))
{
int32_t configStatus = STW_SOK;
OsalRegisterIntrParams_t intrPrms;
OsalInterruptRetCode_e osalRetVal;
HwiP_Handle hwiHandle = NULL;
/* Enable CPU Interrupts and register ISR - MCAN0 Intr0 */
Osal_RegisterInterrupt_initParams(&intrPrms);
/* Populate the interrupt parameters */
intrPrms.corepacConfig.arg = (uintptr_t) NULL;
intrPrms.corepacConfig.isrRoutine = f;
intrPrms.corepacConfig.priority = 0U;
intrPrms.corepacConfig.corepacEventNum = 0U;
intrPrms.corepacConfig.intVecNum = intNum;
/* Register interrupts */
osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
if(OSAL_INT_SUCCESS != osalRetVal)
{
configStatus = CSL_EFAIL;
}
return configStatus;
}
static int32_t App_mcanRegisterIsr(uint32_t mcanInstAddr)
{
int32_t configStatus = STW_SOK;
#if defined (BUILD_MCU1_0)
/* Running Code from Mcu R5 */
/* MCU MCAN Inst 0 */
configStatus = App_mcanRegisterInterrupt(APP_MCU_MCAN_0_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MCU_MCAN_0_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MCU_MCAN_0_TS_INT, &App_mcanTSIntrISR);
/* MCU MCAN Inst 1 */
configStatus += App_mcanRegisterInterrupt(APP_MCU_MCAN_1_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MCU_MCAN_1_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MCU_MCAN_1_TS_INT, &App_mcanTSIntrISR);
#else
/* Running Code from Main R5 */
#if defined (SOC_J721E) || defined (SOC_J7200)
/* Main MCAN Inst 0 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_0_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_0_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_0_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 2 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_2_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 4 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_4_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_4_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_4_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 5 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_5_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_5_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_5_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 6 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_6_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_6_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_6_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 7 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_7_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_7_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_7_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 9 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_9_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_9_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_9_TS_INT, &App_mcanTSIntrISR);
/* Main MCAN Inst 11 */
configStatus = App_mcanRegisterInterrupt(APP_MAIN_MCAN_11_INT0, &App_mcanIntr0ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_11_INT1, &App_mcanIntr1ISR);
configStatus += App_mcanRegisterInterrupt(APP_MAIN_MCAN_11_TS_INT, &App_mcanTSIntrISR);
#endif
#endif
if(STW_SOK != configStatus)
{
UART_printf("CrossBar/Interrupt Configuration failed.\n");
}
else
{
UART_printf("CrossBar/Interrupt Configuration done.\n");
}
return configStatus;
}
Logs:
SBL Revision: 01.00.10.01 (Dec 17 2021 - 09:24:15) TIFS ver: 21.9.1--v2021.09a (Terrific Lla *********************************************** * MCAN Test_FL * *********************************************** CrossBar/Interrupt Configuration done. MCANSS Revision ID: scheme:0x1 Business Unit:0x2 Module ID:0x8e0 RTL Revision:0x9 Major Revision:0x1 Custom Revision:0x0 Minor Revision:0x1 CAN-FD operation is enabled through E-Fuse. Endianess Value:0x87654321 Successfully configured MCAN0 MCANSS Revision ID: scheme:0x1 Business Unit:0x2 Module ID:0x8e0 RTL Revision:0x9 Major Revision:0x1 Custom Revision:0x0 Minor Revision:0x1 CAN-FD operation is enabled through E-Fuse. Endianess Value:0x87654321 Successfully configured MCAN1 Transmitting Data on MCAN Port0 Test Port 0 Sending Packet - 1 1. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 2. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 3. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 Message successfully transferred with payload Bytes:0x8 Port 0 Sending Packet - 2 1. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 2. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 3. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 Message successfully transferred with payload Bytes:0x8 Port 0 Sending Packet - 3 1. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 2. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 3. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 Message successfully transferred with payload Bytes:0x8 Port 0 Sending Packet - 4 1. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 2. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 3. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 Message successfully transferred with payload Bytes:0x8 Port 0 Sending Packet - 5 1. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 2. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 3. TX:CAN ISR row stats: 0, 1fffffff, 0, 1 Message successfully transferred with payload Bytes:0x8 Try Receiving on MCAN port0 1. RX:CAN ISR row stats: 0, 1fffffff, 3fffffff, 3 2. RX:CAN ISR row stats: 0, 1fffffff, 3fffffff, 3 3. RX:CAN ISR row stats: 0, 1fffffff, 3fffffff, 3
Regards
Karan
Hi Karan,
In your code, we can not run, and stay in while(ccs_loop);
This code "while(ccs_loop);" had a problem.
Beside, according to the ISR registration that you modify, I check our TDA4 code, the ISR registration is the same, but our TDA4 still can not trigger ISR function.
Please check this problem again.
Thanks.
BR,
Jay
Hi Jay
1. The while(ccs_loop) is only for debug purpose, you can change the ccs_loop = 0x0.
2. You mention that the ISR registration is the same, do you mean you were already using that or now you modified based on my suggestion and still facing the issue? To make sure that the MCU R5F has the MCAN IP’s interrupt enabled, please check the VIM_INTR_EN_SET_j register value at address 0x40F80408. The value at the 0th bit for this register should be set. This 0th bit corresponds to the MCU R5Fs 0th interrupt which is connected to the MCU MCAN0’s interrupt MCU_MCAN0_MCANSS_MCAN_LVL_INT_0.
VIM register:
Regards
Karan
Hi Karan,
1. Remove while(ccs_loop), TX ISR can work, but RX ISR still can not trigger.(In your log, we don't see RX work well?)
2. do you mean you were already using that or now you modified based on my suggestion and still facing the issue? ==> Yes
I printf the VIM_INTR_EN_SET_j register, the value is 3F. The value at the 0th bit for this register had be set. But our TDA4 code ISR still can not been triggered.
3. In 8.0.2 sample code mcan_evm_loopback_app_main_k3.c, we cannot run normally. Would you provide the mcan_evm_loopback_app_main_k3.c code that can run well on EVM?
Hi Jay
1. Remove while(ccs_loop), TX ISR can work, but RX ISR still can not trigger.(In your log, we don't see RX work well?)
The initial issue was with the TX ISR and that is what I tested. With the changes from my patch you too are now able to see the TX ISR hence I would consider the Tx ISR issue resolved.
3. In 8.0.2 sample code mcan_evm_loopback_app_main_k3.c, we cannot run normally. Would you provide the mcan_evm_loopback_app_main_k3.c code that can run well on EVM?
I used the modified application from you and did not run the default mcan_evm_loopback_app_main_k3.c, let me give this a try.
but RX ISR still can not trigger.(
Can you tell me what is the configuration for the filters on the MCU MCAN0 side? The ISR for Rx will hit only when the incoming message on the CAN bus is intended for the MCU MCAN0 controller i.e. the message ID associated with the message matches the filter configuration for the MCU MCAN0. What is the message ID (and what kind of message - standard ID or extended ID) are you sending from the external CAN emulator & and what is the filter configuration?
Regards
Karan
Closing the loop on this.
The last issue open on this thread for the Rx interrupt was due to internal loopback configuration. With disabling internal loopback, Rx interrupts too are getting triggered.
Regards
Karan
