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TMS320C6678: TMS320C6678 Control Register File Extensions for Floating-Point Operations

Sujitha Anand
Prodigy 10 points
Part Number: TMS320C6678

Hi,

I want to use an event or interrupt when NaN bit is high in FADCR, FMCR, and FAUCR registers. May I know which interrupt or event I can use?

If there is no interrupt exists from these registers, is there any way to turn off the cores when the Nan bit is high in this register? 

Thank you in advance.

  • 0
    TI__Mastermind 25535 points

    Sujitha,

    Rajan is working on your post.

    He will get back to you at the earliest.

  • 0
    TI__Mastermind 25535 points

    Sujitha,

    I would recommend you to have a look at the Interrupts and events section in the data sheet , "https://www.ti.com/lit/ds/symlink/tms320c6678.pdf" 

    We have to use the registers of "CorePac Interrupt Controllers" - CIC0, CIC1, CIC2, CIC3 for configuring the interrupts.

    Extract from the doc: 

    ---

    7.10 Interrupts

    7.10.1 Interrupt Sources and Interrupt Controller

    The CPU interrupts on the C6678 device are configured through the C66x CorePac Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events.

    ---

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 10 points

    Hi Shankari,

    Thanks for the suggestions, But it didn't help much to solve the issue, I could not find the exact interrupt that I can set after division by zero and square root of zero operation.

    - It would be great if you provide some example C code which set interrupts for arithmetic operations. 

    - Please refer "Figure 7-32 TMS320C6678 System Event Inputs — C66x CorePac Primary Interrupts (Sheet 1 of 4)" from "">www.ti.com/.../tms320c6678.pdf"  document and let me know which event I can use for  "Control Register File Extensions for Floating-Point Operations". Thank you.

  • 0 in reply to Sujitha Anand
    Guru 13202 points

    Hello,

    I haven't seen it is possible to trigger interrupt as a consequence of arithmetic operation. That might be pointless as well. Imagine a scenario, where multithreaded OS is running the chip. Once interrupt occurs, it takes number of cycles to detect event, route it to interrupt controller, accept interrupt for processing, switch context and so on. With all those jobs done, one may be several tens of cycles behind the actual cycle, where unsuitable situation happened. Perhaps, core exceptions mechanism is more suitable for that, but 1) their documentation is about the same foggy, 2) never had experience personally. 

    My impression about intended use of those registers is to have user (sub)routines, which perform desired operation and check status of registers immediately afterwards. Nevertheless, would be happy to hear TI'ers input.

    And just in case, if someone would be looking, could you you please decipher, what is

    EFIINTA EFI Interrupt from side A

    EFIINTB EFI Interrupt from side B

    which are C66x CorePack primary input events numbers in user manuals for C6670, C6678.

  • 0 in reply to Sujitha Anand
    TI__Mastermind 25535 points

    Sujitha,

    As far as I know, an interrupt cannot be set/invoked as per the values of  FADCR, FMCR, and FAUCR registers. 

    We have to use the registers of "CorePac Inerrupt Controllers" - CIC0, CIC1, CIC2, CIC3 for configuring the interrupts.

    Some sample code is available as given below to  test the CPINTC Functional layer. The code also utilizes the INTC CSL functional layer to determine that routing of system interrupts to the GEM cores is done properly.

    The name of the file is --- "cpintc_test.c" --- part of CSL ( Chip support library ) example --

    Software package - PROCESSOR-SDK-RTOS-C665x 06_03_00_106

    Link to download : http://software-dl.ti.com/processor-sdk-rtos/esd/C665x/latest/index_FDS.html

    Location of the file after installing the package : \ti\pdk_c665x_2_0_16\packages\ti\csl\example\cpintc.

    Regards

    Shankari G

  • 0 in reply to Victor Kazmirenko
    Prodigy 10 points

    Thanks for the  detailed reply Viktor, It will be great if you give some information regarding where can I find information and example codes for "Error generated interrupts" in TMS320C6678 IC.

  • 0 in reply to Shankari G
    Prodigy 10 points

    Thanks for the detailed reply Shankari, It will be great if you give some information regarding where can I find information and example codes for "Error generated interrupts" in TMS320C6678 IC or in TMS320C66x family..

  • 0 in reply to Sujitha Anand
    TI__Mastermind 25535 points

    ujitha,

    Please refer to this guide on Interrupts and the status of interrupts.

    KeyStone Architecture Literature - Chip Interrupt Controller (CIC) User Guide  https://www.ti.com/lit/ug/sprugw4a/sprugw4a.pdf

    ---

    Would you please help me understand, "what do you mean by error generated interrupts "? 

    Do you mean, To generate or trigger an interrupt when an arithmetic exception is detected ? If yes, there is no option to map with an events or interrupts.

    The same is explained in a detailed way here : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/573031/rtos-tms320c6678-floating-point-exception

    Here, in the below table, no specification about the arithmetic events; Which means, it doesnot exist.

    Regards

    Shankari G