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Hello team
We make a custom board based on J721EX SDK board. After power up sequence(Figure 5-3. Power-Up Sequencing refer to tda4vm document) our software is not launch up.
But injection of Reset signal(MCU_ Resetz) , software is start to launch. It is different to SDK board. What causes do you think?
Many thanks,
Tsutomu Hibino
Tsutomu Hibino
What boot flow are you using? Are you using SBL or SPL/u-boot?
Regards
Karan
We are using SPL/u-boot.
I found that closed issue in this site which certain boards are happen in our development bench.
That means we have seen it which is closed phenomenon.
As a conclusion of this case, is the issue LPDDR layout(hardware)?
LPDDR frequency setting at 4266MTS, is sometime failed, but the setting frequency 3733MTS is fine.
e2e.ti.com/.../tda4vm-spl-failed-to-boot-from-all-boot-devices
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U-Boot SPL 2021.01-g53e79d0e89 (Sep 02 2021 - 18:20:00 +0000)
Model: Texas Instruments K3 J721E SoC
Board: J721EX-PM2-SOM rev E7
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
Trying to boot from MMC2
spl_load_image_fat: error reading image tispl.bin, err - -6
spl_load_image_ext: ext4fs mount err - 0
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Hello Karan
We would like to know why u-boot is not started without MCU_Reset?
And "e2e.ti.com/.../tda4vm-spl-failed-to-boot-from-all-boot-devices" conclusion?
Hardware LPDDR Layout between TDA4VM to LPDDR. Correct?
Many thanks,
Tsutomu Hibino
Hardware LPDDR Layout between TDA4VM to LPDDR. Correct?
Hi,
Which SDK version are you using? Is 3733 MTS working for you?
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1028163/faq-tda4vm-on-7-3-8-0-sdk-how-to-reduce-ddr-speed-to-3733-mts
Can you take a look at the above FAQ to reduce DDR speed to 3733 MTS?
Regards,
Keerthy