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AM6442: AM6442

Part Number: AM6442

Dear all,

we use AM6442 GPMC access FPGA by 32-bit Multiplexed Address/Data synchronize NOR type without  waitpin monitor.

But we  always read 0 no matter FPGA  gpmc region value is 0 or not.below is waveform.

AM6442 ver is PG1.0  we've used.Is this phenomenon right?

thanks,

jimin.li

  • Hello jimin.li,

    Thank you for the query.

    Do you have a diagram to explain the interface ? Is this a custom board ?

    Regards,

    Sreenivasa

  • hi  Kallikuppa Sreenivasa,

    diagram as below.Yes,this is a custom board.

    Do you have a diagram to explain the interface ? Is this a custom board ?

    GPMC interface connection configuration as below:

    AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */
    AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */
    AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */
    AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */
    AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */
    AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */
    AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */
    AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */
    AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */
    AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */

    AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */
    AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */
    AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */
    AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */
    AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */
    AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */

    AM64X_IOPAD(0x00B8, PIN_INPUT, 8) /* (Y7) GPMC0_AD16 */
    AM64X_IOPAD(0x00BC, PIN_INPUT, 8) /* (U8) GPMC0_AD17 */
    AM64X_IOPAD(0x00C0, PIN_INPUT, 8) /* (W8) GPMC0_AD18 */
    AM64X_IOPAD(0x00C4, PIN_INPUT, 8) /* (V8) GPMC0_AD19 */
    AM64X_IOPAD(0x00C8, PIN_INPUT, 8) /* (Y8) GPMC0_AD20 */
    AM64X_IOPAD(0x00CC, PIN_INPUT, 8) /* (V13) GPMC0_AD21 */
    AM64X_IOPAD(0x00D0, PIN_INPUT, 8) /* (AA7) GPMC0_AD22 */
    AM64X_IOPAD(0x00D4, PIN_INPUT, 8) /* (U13) GPMC0_AD23 */
    AM64X_IOPAD(0x00D8, PIN_INPUT, 8) /* (W13) GPMC0_AD24 */
    AM64X_IOPAD(0x00DC, PIN_INPUT, 8) /* (U15) GPMC0_AD25 */
    AM64X_IOPAD(0x00E0, PIN_INPUT, 8) /* (U14) GPMC0_AD26 */
    AM64X_IOPAD(0x00E4, PIN_INPUT, 8) /* (AA8) GPMC0_AD27 */
    AM64X_IOPAD(0x00E8, PIN_INPUT, 8) /* (U9) GPMC0_AD28 */
    AM64X_IOPAD(0x00EC, PIN_INPUT, 8) /* (W9) GPMC0_AD29 */
    AM64X_IOPAD(0x00F0, PIN_INPUT, 8) /* (AA9) GPMC0_AD30 */
    AM64X_IOPAD(0x00F4, PIN_INPUT, 8) /* (Y9) GPMC0_AD31 */

    AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */
    AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */
    AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */
    AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */
    AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */
    AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */
    AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */
    AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */
    AM64X_IOPAD(0x0094, PIN_OUTPUT, 0) /* (P17) GPMC0_BE1n_CLE */
    AM64X_IOPAD(0x00F8, PIN_OUTPUT, 8) /* (V9) GPMC0_BE2n_CLE */
    AM64X_IOPAD(0x014C, PIN_OUTPUT, 8) /* (AA14) GPMC0_BE3n_CLE */
    AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */
    AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */

    GPMC_CONFIG registers configuration as below: 

    GPMC_CONFIG1_0 addr: 0x3B000060

    value: 0x28002200 //burst not support.Read/write synchronous.read/write single access.WAIT pin is not monitored for read/write access.NOR flash like type.device size select 32bit.Address Data multiplex.GPMC CLK frequency = GPMC_FCLK frequency.GPMC_CONFIG2_0 addr: 3B000064 value: 0xF0F00

    GPMC_CONFIG3_0 addr: 3B000068 value: 0x30301
    GPMC_CONFIG4_0 addr: 3B00006C value: 0xF040F04
    GPMC_CONFIG5_0 addr: 3B000070 value: 0xA0F0F
    GPMC_CONFIG6_0 addr: 3B000074 value: 0x8A040000
    GPMC_CONFIG7_0 addr: 3B000078
    value: 0xf52//Chip-select size of 16MB.Cs enable.BASEADDR:010010b
    The waveform is captured when AM6442  read GPMC region:0x52000018 value.
    Thanks,
    jimin.li
  • Hello jimin.li

    Thank you for the input.

    Could you please confirm the development environment you are using. Based on your inputs, i may have to reassign the thread to the expert.

    Regards,

    Sreenivasa

  • hi  Kallikuppa Sreenivasa,

    Thanks,

    ubuntu version is 20.04.

    SDK version is ti-processor-sdk-linux-am64xx-evm-08.02.00.23-Linux-x86

    GPMC driver is in a53 uboot.

    Best regards,

    jimin.li

  • Hello jimin.li

    Thank you for the inputs. 

    Please expect some delay in response as i reassign to the expert.

    Regards,

    Sreenivasa

  • Hi Jimin,

    Sorry I won't be able to help from software perspective. The AM64x Processor SDK Linux v8.2 is not validated with FPGA.

  • Hi Bin,

    Thanks,

    GPMC access to FPGA in SDK linux ver8.2 is not support no matter 32bit or 16bit access?

    Could you tell me which SDK linux version will support FPGA? 

    The AM64x Processor SDK Linux v8.2 is not validated with FPGA.

    Best regards,

    jimin.li

  • hi Bin and Kallikuppa Sreenivasa,

    Yes,we've checked SDK linux ver8.2 source code only  support GPMC NAND access,cause GPMC driver is for NAND.

    Could you kindly tell me if SDK(mcu_plus_sdk & proceesor_sdk_linux) not support FPGA, AM6442 GPMC controller will not support FPGA access?  

    The AM64x Processor SDK Linux v8.2 is not validated with FPGA.

    There is no words say GPMC not support FPGA in AM64x TRM,we also checked issue list about GPMC description in sprz457e-202207-AM64xAM243x Processor Silicon-issuelist.pdf as below.So GPMC 32bit read with NAND and FPGA/FIFO is supported,my understand is right?

     GPMC access FPGA is planning on R5 listed in  sw build sheet as below.

     

    thanks,

    jimin.li

  • Hi Jimin,

    The GPMC controller in AM64x does support accessing FPGA, only the kernel driver has not been validated with FPGA, because currently we don't have an AM64x board with FPGA on it. So we are not sure yet if the kernel GPMC driver requires any modification for accessing FPGA.

  • HI Bin,

    Thanks for your reply.