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Hi
On Faraday DSP TCI6487 we observed that example code with loop back option supplied by TI has different configuration for SRIO registers compared to Host configured values.
We use Host Device to download the code to DSP ( SRIO bootmode ) and not changing any SRIO specific registers in application other than SP registers..
Sequence:
main()
{
CSL_srioInit,
CSL_srioOpen
Block Enable, Doorbell Routing etc
update SP_ERR_RATE, SP_ERR_THRESH and ERR_EN registers in the CSL handle.
}
Also I could see that IP_PRESCAL is setup with value 8 when downloaded. 33 in the example code.
How the DMA clock frequency affect SRIO performance considering DSP works in 1X with 2.5Gbps rate and connected to a switch ?
Also is there any way to monitor SRIO registers for Retransmission failures ? We don't have any probes connected. Only JTAG is connected to DSP. when we connect, code execution stops and we are able to see L2 memory and SRIO related CSL handle register contents.
Adding to the above observation, I do see " Implementation specific error" in SP related registers in SRIO User Guide. But there is no information about these errors mapping to DirectIO / Message Passing or DSP application specific details. How this will help in analysis errors from DSP side ?
When we have set of N transfer for each milli second from DSP to Host over SRIO with Direct IO Message + doorbell with random source addresses, how this can be implemented in DSP.
Currently we form the table and then use EDMA to program LSU registers.
But when any LSU_ICSR error gets generated, EDMA stalls, as LSU errors are routed to ISR to write LSU_REG5 again. But I doubt that 2nd time message transfer will be happening properly.
So how we can tackle LSU errors?
Restart EDMA with current message?
Add one more EDMA channel to store current Table pointer before starting LSU transfer,
and In ISR, program LSU again with new EDMA param?