Hi
On Faraday DSP TCI6487 we observed that example code with loop back option supplied by TI has different configuration for SRIO registers compared to Host configured values.
We use Host Device to download the code to DSP ( SRIO bootmode ) and not changing any SRIO specific registers in application other than SP registers..
Sequence:
main()
{
CSL_srioInit,
CSL_srioOpen
Block Enable, Doorbell Routing etc
update SP_ERR_RATE, SP_ERR_THRESH and ERR_EN registers in the CSL handle.
}
Also I could see that IP_PRESCAL is setup with value 8 when downloaded. 33 in the example code.
How the DMA clock frequency affect SRIO performance considering DSP works in 1X with 2.5Gbps rate and connected to a switch ?
Also is there any way to monitor SRIO registers for Retransmission failures ? We don't have any probes connected. Only JTAG is connected to DSP. when we connect, code execution stops and we are able to see L2 memory and SRIO related CSL handle register contents.