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Dear Expert,
Our customer is doing DDR SI simulation and need to export DDR Timing models (.v file). We want to know how to fill these parameters (CA Timing, CS Timing, CKE Timing, Write Strobe Timing, Write Data Timing). Could you please check that? Thanks.
Best Regards,
Xingyu Zhu
Hi,
Simulating timing of the DDR interface s not supported as far as I am aware - please follow the Jacinto7 LPDDR4 Board Design and Layout Guidlines (link below).
https://www.ti.com/lit/pdf/spracn9
Regards,
Kevin
Correct. As stated in Section 3 of the document Kevin references, the requirement is to perform channel simulations to generate the signal eye diagrams at the targeted Bit Error Rate (BER). The JEDEC defined eye masks are used to determine pass or fail.