Hello,
I'm currently investigating on how to use the different cores of the AM64xx between real time and non real time processing. All cores should access to the Ethernet part with different priorities in both direction (Rx/Tx). Since the real time part need to send frame at high periodic rate (200us / frame), I do not imagine to use the A53 core with Linux to send them (the Treatment should be done in a R5 core). The determinism of ethernet frame should be the best possible to reach that rate to match TSN / TAS requirements and to not miss time slot (one of the multiple reason that I need to achieve the rate of 200us / frame without buffering)
So, when checking over the TI documentation, I found some ideas but not used on the AM64xx chips.
1. The first come from here (https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/ethfw/docs/user_guide/ethfw_c_ug_top.html#ethfw_intercore_r5server). A firmware for R5 seems to be developped to manage a distributed ethernet packets and a linux driver is ready to use.
Such R5 ethernet firmware can be used and available for AM64X as well as linux driver ?
7
CPSW is used here, I supposed it can be easely change to use the PRU-ICSSG since we need support for HSR/PRP
2. I already developped on AM335x chips and PRU-ICSS from that times was able to manage several queues with different priorities. In such case, I was able to use different queue for different cores. As far as I understood, this is not the case anymore right ?
3. I'm open to other suggestion to manage my use case :)
Regards,
Guillaume
