AM5749: DDR3 ECC hardware layout question

Hi,

One initial comment, it looks like the memory connected to the AM57x DDR ECC pins is different than the memories connected to the AM57x DDR data pins. I am unsure where to find the datasheets for these respective parts; however, below is a general statement regarding ECC memory selection.

The DDR memory connected to the DDR ECC bus does NOT need to be the same part number as the DDR memories connected to the DDR data bus. However, some constraints do apply. When selecting a memory for the DDR ECC bus, the following restrictions must be adhered to. Compared to the DDR memories on the data bus, the DDR ECC memory must:

• Match the same DDR type (DDR3, DDR2, etc.) and speed grade
• Have an equal number of internal banks
• Have an equal number of columns
• Have a greater or equal number of rows

In addition,
• Unused pins should be properly tied off as described in the routing guidelines of the device data manual.
• EMIF register settings should be configured to satisfy the larger minimum timing requirements and the smaller maximum timing requirements between the two different DDR memories to ensure that all DDR memories connected to the EMIF channel are running within their specified range.

Let us know if there are any other specific questions you may have; thanks.

Regards,
Kevin