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TDA4VE-Q1: remote sense point placement

Xingyu Zhu
Expert 3625 points
Part Number: TDA4VE-Q1

Dear expert 

TI recommends adopt remote sense to optimize PDN. Given that there are many balls supplied by VDD_CPU/VDD_CORE, is there any detailed advice about the placement of remote sense point? I checked EVM PCB and want know does it recommend to place the sense point in the middle of all balls with same power domain? 

EVM VDD_CPU:

 

EVM VDD_CORE:

Best Regards,

Xingyu Zhu

  • 0
    TI__Mastermind 47440 points

    The goal of the remote sense is to minimize (or eliminate) the IR voltage drop across the PCB.  The sense point should be placed to achieve that goal.  It does not have to be exactly in the center of the processor.  Design goal should be that most of the PCB distance between the SMPS output and the IC ball area is within the remote sense loop.  The VDD_CPU example provided looks good.  I can't tell as clearly on the VDD_CORE example,  but I think its like OK too (assuming RED vias are the VDD_CORE)