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TDA4VE-Q1: DDR placement change

Xingyu Zhu
Expert 3625 points
Part Number: TDA4VE-Q1

Hi expert,

Due to some structure limitation, our customer cannot follow the DDR placement of EVM and have to move one DDR from left side to the bottom side as shown below. Our customer would like to know:

1. they can ensure each DDR satisfy the DDR layout guide. But there is a big length difference between these 2 DDR chips trace. Is there any risk for that? 

2. what's the other comments or suggestions TI can share about their DDR placement?

Best Regards,

Xingyu Zhu

  • +1
    TI__Mastermind 47440 points

    Regarding trace length requirements, there is no relationship between the two DDR interfaces.  They are independent.  TI has not done any evaluation of the proposed placement for the DDR memory device and its unclear what routing challenges will arise due to the placement.  Recommendation is to follow the Jacinto7 LPDDR4 guidelines, and minimize any deviation.  Trace lengths will likely increase beyond those recommended, and customer will have to decide to take those risks.  Its possible bus frequency will need to be relaxed - again depending on the amount of deviation from our reference.