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66AK2G12: DDR PLACEMENT ANALYSIS

babu peeraiah
Prodigy 90 points
Part Number: 66AK2G12

Hello 

We are interfacing DDR3L 512MB to a keystone processor. We have a total of 3 DDR chips two DDR chips on the top side and one DDR chip on the bottom side.
We have placed ECC DDR and DDR  number 2 (D16-D31)  exactly on top of each other in a mirrored fashion.
DDR number 1(D0-D15) is placed separately on the topside (the side of DDR no 2), please refer to the image attached.
we have gone with this kind of approach due to space constraints.

we are planning to route the address and command line in a daisy chain fashion,
According to our signal integrity team, the current DDR placement involves a combination of the daisy chain and star topology which is a hybrid topology.

Has this kind of placement approach been practically verified by any of the designers?


Should we take any extra precautions during routing or termination with this kind of placement approach?

Regards
Babu

  • +1
    TI__Guru* 80020 points

    Can you clarify the topology?  At first you say the addr/ctrl will be a fly-by topology, but then you say you are using a star topology.  The addr/ctrl signals should be routed in a fly-by topology, and terminated at the end to VTT.  The data signals will be point to point.  It is not recommended to deviate from this topology for DDR3.  You can get a lot of design guidance in this app note:  https://www.ti.com/lit/pdf/sprabi1

    REgards,

    James