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66AK2G12: DDR CLOCK

babu peeraiah
Prodigy 90 points
Part Number: 66AK2G12

Hello 

I am designing a board with 66AK2G12ABYA100E, in EVM schematics DDR CLK is fed from CDCM  100Mhz lvds signals, and soc datasheet    tells DDR clock range of 24,25Mhz 

what is the DDR clock to be fed to soc, and can we use the DDR clock generated internally of soc from SYSOSC CLK from crystal externally.

in the power-on sequence of processor attached in the image,  the highlighted DDR_CLK_P and DDR_CLK_N should follow the sequence if the DDR CLK is generated internally from SYSOSC CLK fromcrystal or no?

Please guide me with ddr clocking

  • 0
    TI__Guru* 80170 points

    You can choose to use an internal or external clock for DDR with the  DDR_CLK_MUXSEL bit in BOOT_CFG_DDR_CLKCTL register.  See table 5-504 and table 5-267 in the TRM

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 90 points

    Thank you James for the Reply

    I understand that we can  use the external oscillator clock for the main system clock and the DDR clock,

    there were a few more queries in my previous question, request to please clarify the same

    • IN EVM CDCM generates a clock for  DDR that is 100Mhz and by using an internally generated DDR clock is 24MHz, how is there a difference in the DDR frequency fed to soc ddr block, what is the correct frequency to be fed.
    • I understand that the sequencing for DDR CLK is not required when generated internally from sysclk, is my understanding correct.
    • I am driving my soc with only an external oscillator clock of 24Mhz, so we will drive the DDR clk with the same, hope with the power sequencing correct and sysclk available before PORn the system will come up smoothly. now after soc comes up, now I will program my cdcm from my soc, My question in this  point is presently soc and DDR(internally generated ) is driven by external crystal and if I drive this soc clock and DDR CLK from CDCM and change my SYSCLSEL pin and after giving PORn ,will soc work correctly without any issue.
    • to summarize 3 point, the first soc will come up with a crystal and once the soc wakes up,i will program cdcm and change the source of the clks to cdcm ,will the soc function smoothly.

    Regards
    babu
    8105939434

  • +1 in reply to babu peeraiah
    TI__Guru* 80170 points

    -the max frequency for the DDR PLL is defined in the datasheet, depending on your device speed grade, see Table 5-1 in the datasheet.  You would program the DDR PLL accordingly.  The optional DDR_CLK_P/N input requirements are also in the datasheet in table 5-18.  I'm not sure why it is labeled as 100MHz in the schematic, this is beyond the datasheet limitations

    -Yes there is no sequencing requirements when generating the clock internally, as the clock would be started in your boot code, and then the DDR is initialized

    -you don't need to drive the DDR_CLK_P/N from CDCM, if you are driving the clock from the DDR PLL.  Ensure DDR_CLK_MUXSEL=0 to use the internal DDR PLL

    Regards,

    James